一種新的集成電路互連線串?dāng)_模型和估計(jì)公式
A new kind of interconnect crosstalk model and estimation formula for high-speed integrated circuits
-
摘要: 建立了一個(gè)考慮分布電阻，分布電容的互連線混П模型，在這個(gè)模型的基礎(chǔ)上，分析了終端在最壞條件下的串?dāng)_響應(yīng)，并推導(dǎo)了三階S域系數(shù)的精確表達(dá)式，最終，獲得了一個(gè)新的互連線串?dāng)_響應(yīng)的估計(jì)公式，通過(guò)與SPICE模擬的結(jié)果相比較，該文的模擬結(jié)果非常接近實(shí)際電路的串?dāng)_響應(yīng)，與相關(guān)文獻(xiàn)所發(fā)表的結(jié)果相比較，該模型更符合實(shí)際情況，結(jié)果也更精確。Abstract: In this paper, an interconnect delay estimation model is built up, including the effect of distributed resistance, capacitance and even inductance. Then, on the basis of this model, the respondence of the terminal on the worst condition is analyzed and three-order precise formula to estimate the crosstalk respondence is presented. In the end, a new estimation formula for interconnect crosstalk respondence is derived. Moreover, experimental result is excellent enough to the simulation result of SPICE for practical circuit.
-
Y. Eo, W. R. Eisenstadt, J. Y. Jeong, O. Kwon, A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design, IEEE Trans. on Electron Devices, 2000,47(1), 129-140.[2]T. Sakurai, Closed-form expressions for interconnection delay, coupling and crosstalk in VLSIs,IEEE Trans. on Electron Devices, 1993, 40(1), 118-124.[3]J. Cong , Z. Pan, Interconnect delay estimation models for synthesis and design planning, in Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, 97-100.[4]Y.I. Ismail, E. G. Friedman, J. L. Neves, Figures of merit to characterized the important of on-chip inductance, IEEE Trans. on VLSI Syst. 1999, 7(4), 442-449.[5]Semiconductor Industry Association, National Technology Roadmap for Semiconductor, USA,1997. -
計(jì)量
- 文章訪問數(shù): 2509
- HTML全文瀏覽量: 95
- PDF下載量: 436
- 被引次數(shù): 0
下載:
