nMOS四值觸發(fā)器的設計及其應用
THE DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS
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摘要: 本文應用限幅電壓開關理論設計了兩種主從型nMOS四值觸發(fā)器。這砦觸發(fā)器具有雙端預置能力和雙軌互補輸出。通過采用JKLM型觸發(fā)器對十六進制加法計數器和十進制加法計數器的設計實例證明了這些觸發(fā)器能有效地用于四值時序電路的設計。Abstract: By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed.These flip-flops have the capability of two-input presetting and double-rail complementary outputs. A modulo-16 up counter and a modulo-10 up counter are designed by using JKLM type flip-flop. It is shown that these flip-flops can be flexibly used to design quaternary sequential circuits.
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吳訓威,陳偕雄.具有三軌輸出的三值維持阻塞觸發(fā)器的研究.科學通報,1986, 31(16): 1380-1383.[2]Xunwei Wu. The theory of clipping voltage-switches and design of quaternary nMOS circuits. IEEE[3]Proc. ISMVL, Sendai: 1992, 119-102.[4]吳訓威.指導nMOS電路元件級設計的開關信號理論.電子學報,1993, 21(1): 83-86.[5]Xunwei Wu, Xiaojie Zhao. Design of ternary nMOS circuits based on theory of clipping voltage switches. Int. J. Electronics, 1993, 74(1): 91-102.[6]Vranesic Z B. Multiple-valued logic: An introduction and overiew[J].IEEE Trans. on Computer.1977, C-26(12):1181-1182[7]吳訓威.多值邏輯電路設計原理.杭州:杭州大學出版社,1994,19-25.[8]Yasuda Y, et al. Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. of SSC., 1986, SC-21(1): 162-168.[9]吳訓威,陳其翔.雙端置數技術與高值CMOS觸發(fā)器設計.電子科學學刊,1994, 16(1): 91-95.[10]吳訓威,陳偕雄.具有三軌輸出的三值觸發(fā)器及其在三值時序電路中的應用.中國科學(A輯), 1985, (7): 643-654.[11]吳訓威,畢德祥.對基于模代數的三值觸發(fā)器的研究.電子學報,1984, 12(3): 6-13. -
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