寬帶數(shù)字下變頻的一種高效實(shí)現(xiàn)結(jié)構(gòu)
An Efficient Implementation Architecture for Wideband Digital Downconversion
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摘要: 寬帶數(shù)字接收系統(tǒng)要以大的調(diào)諧帶寬截獲窄帶信號(hào),要求數(shù)字下變頻器具有高的數(shù)據(jù)率和快的調(diào)諧時(shí)間,現(xiàn)有的商用數(shù)字下變頻器不能滿(mǎn)足這些要求。本文提出一種高效實(shí)現(xiàn)結(jié)構(gòu),綜合利用DFT濾波器的靈活性和多相濾波的高效性,按照先抽取數(shù)據(jù),再低通濾波、混頻的順序,較好地解決了硬件速度和高速數(shù)據(jù)流不匹配的問(wèn)題。計(jì)算機(jī)模擬結(jié)果證明了處理結(jié)構(gòu)的有效性。
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關(guān)鍵詞:
- 數(shù)字下變頻; 寬帶數(shù)字接收; 多相濾波
Abstract: The wideband digital receiver systems require DDC with high speed and short tuning time in order to intercept narrowband signal in broad tuning bandwidth. However, these requirements can not be met by the commercial DDC. In this paper an efHcient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution of the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture. -
宗孔德,多抽樣率信號(hào)處理,北京,清華大學(xué)出版社,1996年7月,47-50.[2]J. Fudge, M. Legako, C. Sehreiner, An approach to efficient wideband digital downconversion, Proc. ICSPAT, Toronto, Canada, 1998, 713-717.[3]R.G. Vaughan, N. L. Scott, D. R. White, The theory of bandpass sampling, IEEE Trans. on SP, 1991, SP-39(9), 1973-1984.[4]D.R. Zahirniak, D. L. Sharpin, T. W. Fields, A hardware-efficient multirate digital channelized receiver architecture, IEEE Trans. on AES, 1998, AES-34(1), 137-151.[5]R. Baines, The DSP bottleneck, IEEE Communications Magazine, 1995, 33(5), 46-54. -
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