面向通用處理器芯粒架構(gòu)探索和評(píng)估的系統(tǒng)級(jí)模擬器

張聰武; 劉澳; 張科; 常軼松; 包云崗

doi:10.11999/JEIT240299

面向通用處理器芯粒架構(gòu)探索和評(píng)估的系統(tǒng)級(jí)模擬器

doi: 10.11999/JEIT240299 cstr: 32379.14.JEIT240299

張聰武^{1, 2},
劉澳^{1, 3},
張科^{1, 2, ,},
常軼松^{1, 2},
包云崗^{1, 2}

1.
中國(guó)科學(xué)院計(jì)算技術(shù)研究所處理器芯片全國(guó)重點(diǎn)實(shí)驗(yàn)室北京 100190
2.
中國(guó)科學(xué)院大學(xué)計(jì)算機(jī)科學(xué)與技術(shù)學(xué)院北京 100049
3.
鄭州大學(xué)河南先進(jìn)技術(shù)研究院鄭州 450003

基金項(xiàng)目: 中國(guó)科學(xué)院戰(zhàn)略性先導(dǎo)科技專項(xiàng)(XDA0320000, XDA0320300)，國(guó)家自然科學(xué)基金重大項(xiàng)目(62090020)

詳細(xì)信息

作者簡(jiǎn)介:
張聰武：男，博士生，研究方向?yàn)轶w系結(jié)構(gòu)模擬器和異構(gòu)計(jì)算

劉澳：男，碩士生，研究方向?yàn)轶w系結(jié)構(gòu)模擬器和PCIe

張科：男，博士，正高級(jí)工程師，研究方向?yàn)橛?jì)算機(jī)體系結(jié)構(gòu)、異構(gòu)加速、FPGA云

常軼松：男，博士，高級(jí)工程師，研究方向?yàn)橛?jì)算機(jī)體系結(jié)構(gòu)和異構(gòu)計(jì)算

包云崗：男，博士，研究員，研究方向?yàn)閿?shù)據(jù)中心體系結(jié)構(gòu)、處理器芯片敏捷設(shè)計(jì)方法論、開源處理器芯片生態(tài)

通訊作者:
張科　zhangke@ict.ac.cn

中圖分類號(hào): TN4; TN319
計(jì)量
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- 被引次數(shù): 0
出版歷程
- 收稿日期: 2024-04-19
- 修回日期: 2024-11-11
- 網(wǎng)絡(luò)出版日期: 2024-11-19
- 刊出日期: 2024-12-01

A System-level Exploration and Evaluation Simulator for chiplet-based CPU

ZHANG Congwu^{1, 2},
LIU Ao^{1, 3},
ZHANG Ke^{1, 2
, ,},
CHANG Yisong^{1, 2},
BAO Yungang^{1, 2}

1.
State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
2.
School of Computer Science and Technology, University of Chinese Academy of Sciences, Beijing 100049, China
3.
Henan Institute of Advanced Technology, Zhengzhou University, Zhengzhou 450003, China

Funds: The Strategic Priority Research Program of Chinese Academy of Sciences (XDA0320000, XDA0320300), The MajorProgram of the National Natural Science Foundation of China (62090020)

摘要

摘要: 隨著摩爾定律的逐步失效，芯片制造工藝的提升愈發(fā)困難，芯片性能的提升面臨“面積墻”問題，chiplet(芯粒)技術(shù)開始被廣泛采用來解決此問題。然而，面向chiplet引入的架構(gòu)設(shè)計(jì)參數(shù)，目前的體系結(jié)構(gòu)模擬器面臨新的挑戰(zhàn)。為了能夠探索chiplet架構(gòu)的特定設(shè)計(jì)參數(shù)，現(xiàn)有工作通常只會(huì)為模擬器增加單一的功能，導(dǎo)致其難以用于探索多個(gè)參數(shù)對(duì)chiplet芯片的整體影響。為了能夠較為全面地探索和評(píng)估chiplet芯片架構(gòu)，該文基于現(xiàn)有g(shù)em5模擬器實(shí)現(xiàn)了面向通用處理器芯粒架構(gòu)探索和評(píng)估的系統(tǒng)級(jí)模擬器(SEEChiplet)模擬器框架。首先，總結(jié)了現(xiàn)在chiplet芯片設(shè)計(jì)關(guān)注的3類設(shè)計(jì)參數(shù)，包括：(1) 芯片cache系統(tǒng)設(shè)計(jì)；(2) 封裝方式模擬；(3) chiplet間的互連網(wǎng)絡(luò)。其次，針對(duì)上述3類參數(shù)：(1)設(shè)計(jì)并實(shí)現(xiàn)了私有末級(jí)緩存系統(tǒng)，擴(kuò)大了cache系統(tǒng)設(shè)計(jì)空間；(2) 修改了gem5已有的全局目錄，以適配私有末級(jí)緩存(LLC)系統(tǒng)；(3) 建模了兩種常見的chiplet封裝方式以及chiplet間互連網(wǎng)絡(luò)。最后，該文在SEEChiplet框架中進(jìn)行了系統(tǒng)級(jí)的模擬評(píng)估，在被測(cè)chiplet架構(gòu)通用處理器上運(yùn)行操作系統(tǒng)及PARSEC 3.0基準(zhǔn)測(cè)試程序，驗(yàn)證了SEEChiplet的功能，證明SEEChiplet可以對(duì)chiplet設(shè)計(jì)空間進(jìn)行探索和評(píng)估。
- 芯粒 /
- 設(shè)計(jì)空間探索 /
- 體系結(jié)構(gòu)模擬器 /
- 緩存系統(tǒng)
Abstract: As Moore’s Law comes to an end, it is more and more difficult to improve the chip manufacturing process, and chiplet technology has been widely adopted to improve the chip performance. However, new design parameters introduced into the chiplet architecture pose significant challenges to the computer architecture simulator. To fully support exploration and evaluation of chiplet architecture, System-level Exploration and Evaluation simulator for Chiplet (SEEChiplet), a framework based on gem5 simulator, is developed in this paper. Firstly, three design parameters concerned about chiplet chip design are summarized in this paper, including: (1) chiplet cache system design; (2) Packaging simulation; (3) Interconnection networks between chiplet. Secondly, in view of the above three design parameters, in this paper: (1) a new private last level cache system is designed and implemented to expand the cache system design space; (2) existing gem5 global directory is modified to adapt to new private Last Level Cache (LLC) system; (3) two common packaging methods of chiplet and inter-chiplet network are modeled. Finally, a chiplet-based processor is simulated with PARSEC 3.0 benchmark program running on it, which proves that SEEChiplet can explore and evaluate the design space of chiplet.
- Chiplet /
- Design space exploration /
- Computer architecture simulator /
- Cache system

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圖 1 傳統(tǒng)芯片結(jié)構(gòu)和眾核chiplet結(jié)構(gòu)對(duì)比

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圖 2 兩種眾核chiplet cache系統(tǒng)(以內(nèi)存容量8GB為例)

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圖 3 chiplet集成方式

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圖 4 gem5片上網(wǎng)絡(luò)連接模型

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圖 5 SEEChiplet整體框架

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圖 6 chiplet私有末級(jí)緩存系統(tǒng)建模以及讀寫請(qǐng)求處理流程

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圖 7 全局目錄建模及讀寫請(qǐng)求處理流程示意

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圖 8 不同封裝方式的實(shí)現(xiàn)方案

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圖 9 IO-Die和Mesh拓?fù)?/p>

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圖 10 模擬環(huán)境下不同拓?fù)鋮?shù)下基準(zhǔn)測(cè)試程序運(yùn)行時(shí)間

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圖 11 16chiplet不同核數(shù)不同拓?fù)?，blackscholes程序運(yùn)行的平均包延遲

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圖 12 16chiplet不同核數(shù)配置下，blackscholes基準(zhǔn)測(cè)試程序在模擬環(huán)境運(yùn)行時(shí)的平均包跳數(shù)

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表 1 眾核chiplet架構(gòu)設(shè)計(jì)空間

設(shè)計(jì)選項(xiàng)	參數(shù)數(shù)量
chiplet本身	處理器：指令集架構(gòu)；順序執(zhí)行，亂序執(zhí)行；核心數(shù)量 cache系統(tǒng)：cache 塊大?。籧ache容量；cache層級(jí)；chiplet私有末級(jí)緩存，全局共享末級(jí)緩存等 chiplet數(shù)量
chiplet互連架構(gòu)	chiplet拓?fù)洌篗esh, IO-die等；路由算法 chiplet互連：連接帶寬；連接延遲；Router延遲 chiplet集成方式：MCM, 2.5D, 3D；chiplet與封裝基板或中介層(Interposer)間SERDES配置等

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表 2 現(xiàn)有chiplet研究工作

研究工作	基于的模擬器或模擬手段	研究?jī)?nèi)容	chiplet封裝方式	是否支持模擬運(yùn)行操作系統(tǒng)	是否開源
Meduza^[16]	PriME^[24]	chiplet cache系統(tǒng)	2.5D	否	否
文獻(xiàn)[17]	gem5^[25]	chiplet cache系統(tǒng)	2.5D	否	否
文獻(xiàn)[18]	Multi2Sim^[26]	chiplet cache系統(tǒng)	無線連接	否	否
文獻(xiàn)[19]	gem5-X^[27]	chiplet cache 系統(tǒng)	無線連接	是	否
1-Update^[20]	SimFlex^[28]	chiplet cache系統(tǒng)	3D	否	是
SILO^[21]	未提到	chiplet cache系統(tǒng)	3D	否	否
Kite^[22]	gem5	chiplet 拓?fù)?/td>	2D, 2.5D	是	否
HexaMesh^[23]	BookSim^[29]	chiplet 拓?fù)?/td>	2.5D	否	否
文獻(xiàn)[30]	Swarm^[31]	chiplet 架構(gòu)性能	2D, 2.5D	否	否
文獻(xiàn)[32]	gem5^[24]	chiplet 架構(gòu)模擬	無	是	是
DCRA^[33]	muchiSim^[34]	chiplet 架構(gòu)模擬	2D, 2.5D	否	是
文獻(xiàn)[35]	FPGA	chiplet 架構(gòu)模擬	2D	是	否
SMAPPIC^[36]	FPGA	chiplet 架構(gòu)模擬	無	是	是

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表 3 chiplet模擬器相關(guān)工作比較

chiplet模擬工作	全系統(tǒng)模擬	chiplet集成	cache系統(tǒng)	chiplet間網(wǎng)絡(luò)
文獻(xiàn)[32]	×	×	×	√
muchiSim^[34]	×	×	×	√
文獻(xiàn)[35]	×	√	×	×
SMAPPI^C[36]	√	×	√	×
SIAM^[37]	×	×	×	√
SEEChiplet	√	√	√	√

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表 4 SEEChiplet模擬參數(shù)配置表

配置項(xiàng)	基本信息
CPU	Timing CPU, X86指令集，3 GHz
cache層級(jí)及相應(yīng)參數(shù)(其中容量等參數(shù)可以根據(jù)用戶需求配置)	3級(jí)cache, Inclusive，頻率同CPU L1: 指令cache，數(shù)據(jù)cache；每個(gè)CPU核心一組；均為32 kB, 4路組相連 L2: 每個(gè)CPU一組；1MB, 8路組相連 L3：所有chiplet共享/chiplet內(nèi)部共享；32 MB, 16路組相連
封裝方式	MCM, 2.5D：SERDES組件增加2個(gè)cycle, Router本身3個(gè)cycle
chiplet拓?fù)?/td>	支持IO Die, Mesh架構(gòu)
chiplet參數(shù)	每個(gè)chiplet可以有2, 4, 8, 16個(gè)核心
內(nèi)存	單通道DDR4, 8 GB, 2400 MT/s

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表 5 不同末級(jí)緩存架構(gòu)，chiplet內(nèi)外部請(qǐng)求分布

末級(jí)緩存組織形式	內(nèi)部請(qǐng)求比例(%)	外部請(qǐng)求比例(%)	請(qǐng)求總數(shù)量
chiplet私有末級(jí)緩存	78.4	21.6	458037
全局共享末級(jí)緩存	5.8	94.2	404340

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表 6 SEEChiplet建模開銷總結(jié)

開銷來源	開銷總結(jié)
chiplet私有末級(jí)緩存	代碼量：～1000行新增中間狀態(tài)：12個(gè) 新增事件類型：11個(gè) 新增狀態(tài)轉(zhuǎn)移邏輯：30個(gè)，和全局目錄及其他LLC進(jìn)行交互新增虛通道：2個(gè)，用于和全局目錄進(jìn)行交互
全局目錄	代碼量：～600行每行新增bit數(shù)：64bit用于存放共享chiplet列表， 8 bit用于存放持有者chiplet ID 新增狀態(tài)：1個(gè)基礎(chǔ)狀態(tài)S, 9個(gè)中間狀態(tài) 修改狀態(tài)：M狀態(tài)以及相關(guān)處理邏輯新增事件類型：10個(gè)
全局目錄	新增狀態(tài)轉(zhuǎn)移邏輯：18個(gè)，全局目錄轉(zhuǎn)發(fā)請(qǐng)求，響應(yīng)請(qǐng)求等新增虛通道：2個(gè)，用于和末級(jí)緩存進(jìn)行交互

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