應(yīng)用于數(shù)字DC-DC轉(zhuǎn)換器的高分辨率數(shù)字脈寬調(diào)制器設(shè)計
doi: 10.11999/JEIT190482 cstr: 32379.14.JEIT190482
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合肥工業(yè)大學(xué)電子科學(xué)與應(yīng)用物理學(xué)院 合肥 230601
基金項目: 國家自然科學(xué)基金(61674049)，中央高校基本科研業(yè)務(wù)費(PA2018GDQT0017, JZ2019HGTB0092)，中國科學(xué)院蘇州納米技術(shù)與納米仿生研究所納米器件與應(yīng)用重點實驗室開放基金(18ZS03)
High Resolution Digital Pulse Width Modulation Design for Digital DC-DC Converter
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Institute of Electronic Science & Applied Physics, HeFei University of Technology, Hefei 230601, China
Funds: The National Natural Science Foundation of China (61674049), The Fundamental Research Funds for Central Universities (PA2018GDQT0017, JZ2019HGTB0092), The Key Laboratory of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, CAS (18ZS03)
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摘要: 數(shù)字控制在電力電子領(lǐng)域的優(yōu)勢使得數(shù)字脈沖寬度調(diào)制的使用日益增加，然而其分辨率不足一直是制約開關(guān)電源領(lǐng)域中數(shù)字控制技術(shù)發(fā)展的主要因素之一。針對高分辨率數(shù)字脈沖寬度調(diào)制的應(yīng)用需求，該文提出一種基于高速進(jìn)位鏈結(jié)構(gòu)的高分辨率數(shù)字脈沖寬度調(diào)制電路。該電路采用計數(shù)器、比較器、固定相移鎖相環(huán)單元及高速進(jìn)位鏈的混合結(jié)構(gòu)，有效地提高了分辨率，并在Altera的Cyclone IV低成本現(xiàn)場可編程門陣列器件上實現(xiàn)。實驗結(jié)果顯示，當(dāng)輸入?yún)⒖紩r鐘工作頻率為70 MHz時，該結(jié)構(gòu)的分辨率可達(dá)到56 ps。此外，該電路還具有較寬的開關(guān)頻率調(diào)節(jié)范圍及較好的線性度等優(yōu)點。
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關(guān)鍵詞:
- 數(shù)字脈沖寬度調(diào)制 /
- 高分辨率 /
- 數(shù)字控制 /
- 現(xiàn)場可編程門陣列
Abstract: The advantages of digital control in the field of power electronics lead to an increasing use of Digital Pulse Width Modulation (DPWM). However, the insufficient resolution of DPWM is one of the main factors that constrain the development of digital control technology in the field of switch mode power supplies. For the application requirements of high-resolution DPWM, this paper proposes a high-resolution DPWM circuit based on high-speed carry chain structure. The circuit comprises of counters, comparators, fixed phase shift PLL units and high-speed carry chains, which can effectively increase resolution. The circuit is also implemented on Altera’s Cyclone IV low-cost Field-Programmable Gate Array (FPGA) devices. The experimental results show that the resolution of the structure can reach 56 ps with 70 MHz input reference clock. In addition, the circuit also has wide switching frequency adjustment range and good linearity. -
表 1 輸入數(shù)據(jù)流信號duty對應(yīng)的輸出理想延遲時間和輸出占空比命令
${\bf{duty}}\left( {{{M}} - {\bf{1:0}}} \right)$ $ {{t}}_{\bf{D}} $ ${{D} }_{{K} }{{D} }_{ { {{K} }{\rm{-} }1} }···{{D} }_{\bf{1} }{{D} }_{\bf{0} }$ 00···000 0 10000···00 00···001 $ {t}_{\rm{c}} $ $ 01000···00 $ 00···010 $ 2{t}_{\rm{c}} $ $ 00100···00 $ $. $ $. $ $. $ $. $ $. $ $. $ $. $ $. $ $. $ 11···111 $ K{t}_{\rm{c}} $ $ 00000···01 $ 
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