低熱梯度導(dǎo)向的三維FPGA互連通道網(wǎng)絡(luò)架構(gòu)研究
doi: 10.11999/JEIT181134 cstr: 32379.14.JEIT181134
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1.
中國(guó)科學(xué)院電子學(xué)研究所 北京 100190
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2.
中國(guó)科學(xué)院大學(xué) 北京 100049
基金項(xiàng)目: 國(guó)家自然科學(xué)基金(61876172, 61704173)，北京市科技重大專項(xiàng)課題(Z171100000117019)
Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design
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1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
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2.
University of Chinese Academy of Sciences, Beijing 100049, China
Funds: The National Natural Science Foundation of China (61876172, 61704173), The Major Program of Beijing Science and Technology (Z171100000117019)
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摘要: 該文針對(duì)3維FPGA (3D FPGA)芯片存在的散熱問(wèn)題，提出具有低熱梯度特征的互連網(wǎng)絡(luò)通道結(jié)構(gòu)，力圖解決傳統(tǒng)FPGA勻稱互連通道設(shè)計(jì)在芯片堆疊實(shí)現(xiàn)上產(chǎn)生的溫度非平衡現(xiàn)象。該文建立了3D FPGA的熱阻網(wǎng)絡(luò)模型；對(duì)不同類型的通道線對(duì)3D FPGA的熱分布影響進(jìn)行了理論分析和熱仿真；提出了垂直方向通道網(wǎng)絡(luò)非均勻分布的3D FPGA通道結(jié)構(gòu)，實(shí)驗(yàn)表明，與給定傳統(tǒng)FPGA互連通道結(jié)構(gòu)相比，采用所提方法實(shí)現(xiàn)的3D FPGA設(shè)計(jì)架構(gòu)能夠降低76.8%的層間最高溫度梯度，10.4%的層內(nèi)溫度梯度。
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關(guān)鍵詞:
- 3維現(xiàn)場(chǎng)可編程門(mén)陣列 /
- 非均勻通道結(jié)構(gòu) /
- 熱分布
Abstract: To solve the problem of heat dissipation in Three Dimensional Field Programmable Gate Array Technology (3D FPGA), an interconnect channel architectural design method with low thermal gradient feature is proposed. A thermal resistance network model is established for the 3D FPGA, and theoretical studies and thermal simulation experiments are carried out on the influence of different types of channels on the thermal performance of 3D FPGA. Further, non-uniform vertical direction channel structures of 3D FPGA are proposed. Experiments indicate that 3D FPGA designed using the method proposed can reduce the maximum temperature gradient between different layers by 76.8% and the temperature gradient within the same layer by 10.4% compared with the traditional channel structure of 3D FPGA. -
表 2 封裝材料設(shè)置
部件 材料 尺寸 切片 Si 8 mm×6 mm TSV Cu 直徑：20 μm，高度：50 μm Micro-Bump (微凸塊) Cu 高度：20 μm Ceramic substrate (陶瓷襯底) 氧化鋁 30 mm×30 mm BGA solder ball (BGA焊球) Sn63/Pb37 直徑：0.6 mm，中心距：1 mm PCB motherboard (PCB板) FR4 30 mm×30 mm 
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表 3 新結(jié)構(gòu)熱分析統(tǒng)計(jì)結(jié)果
最低溫度(°C) 最高溫度(°C) 平均溫度(°C) 切片1 40.9203 45.1598 43.6753 切片2 41.7091 45.2051 43.9975 切片3 42.1229 45.2337 44.1000 切片4 42.3739 45.2715 44.2322
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表 4 層間熱梯度改善情況
最低溫度梯度
(°C)最高溫度梯度
(°C)平均溫度梯度
(°C)傳統(tǒng)結(jié)構(gòu) 1.4601 0.4824 0.6717 新結(jié)構(gòu) 1.4536 0.1117 0.5569 改善比例(%) 0.4 76.8 17.1
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表 5 層內(nèi)熱梯度改善情況
切片1 切片2 切片3 切片4 傳統(tǒng)結(jié)構(gòu)溫度差(°C) 4.2112 3.6969 3.3647 3.2335 新結(jié)構(gòu)溫度差(°C) 4.2395 3.4960 3.1108 2.8976 改善比例(%) –0.60 5.40 7.50 10.40
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