基于數(shù)字鎖相環(huán)的星載光譜儀本地時鐘源設計
doi: 10.11999/JEIT170088 cstr: 32379.14.JEIT170088
基金項目:
國家自然科學基金(41275037)，安徽省杰出青年科學基金(1308085JGD03)
Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop
Funds:
The National Natural Science Foundation of China (41275037), Anhui Province Outstanding Youth Science Foundation (1308085JGD03)
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摘要: 該文針對太陽同步軌道衛(wèi)星由于通訊誤碼導致衛(wèi)星時鐘不正常翻轉(zhuǎn)造成的錯誤，提出了糾錯策略?；谛l(wèi)星時鐘和本地時鐘授時誤差互補的特點，設計了一種應用于低頻輸入信號和大倍頻系數(shù)條件下的數(shù)字鎖相環(huán)(DPLL)，利用數(shù)字鎖相環(huán)使本地時鐘跟蹤衛(wèi)星時鐘秒脈沖的相位波動，實時消除本地時鐘的累積誤差。對該時鐘源進行了理論分析和實驗驗證，用現(xiàn)場可編程門陣列(FPGA)予以實現(xiàn)。實驗表明，該設計實現(xiàn)的時鐘源可以實時糾正衛(wèi)星時鐘出現(xiàn)的秒脈沖不正常翻轉(zhuǎn)、秒脈沖丟失、時間包跳變、時間包丟失等錯誤，最短可以在5個輸入時鐘周期內(nèi)進入鎖定狀態(tài)，穩(wěn)定工作時每秒累積誤差小于100 s，可作為星載光譜儀本地時鐘源使用。
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關鍵詞:
- 數(shù)字鎖相環(huán) /
- 反饋控制 /
- 比例積分控制 /
- 倍頻 /
- FPGA
Abstract: Under the condition of working in sun-synchronous orbit, the error correction strategy is put forward due to the error caused by the communication error. According to the complementary error characteristics between satellite clock and local clock, a Digital Phase Locked Loop (DPLL) is designed, which is applied to the low frequency input signal and the large frequency multiplication factor. The local clock tracks the satellite clock pulse phase fluctuations and eliminates the accumulate error constantly. The complete design is developed with Field Programmable Gate Array (FPGA) devices and the detailed theoretical analysis and experimental results are presented. Experiments show that the design of the clock source can correct the abnormal flip or lose of second pulse and jump or lose of broadcast time package constantly. It can enter the lock state in 5 input clock cycles, and the cumulative error is less than 100 s. It can be used as the local clock source of satellite borne equipment. -
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