基于縮短極化碼的MLC NAND Flash差錯控制技術研究

郭銳; 王美潔; 王杰

doi:10.11999/JEIT160864

基于縮短極化碼的MLC NAND Flash差錯控制技術研究

doi: 10.11999/JEIT160864 cstr: 32379.14.JEIT160864

基金項目:

浙江省自然科學基金(LY16F010013)，浙江省重點科技創(chuàng)新團隊基金(2013TD03)，國家自然科學基金(61401130)

計量
- 文章訪問數(shù): 1733
- HTML全文瀏覽量: 231
- PDF下載量: 306
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2016-08-22
- 修回日期: 2017-01-12
- 刊出日期: 2017-07-19

Research on the MLC Nand Flash Error Control Technology Based on Polar Codes

Funds:

The Natural Science Foundation of Zhejiang Province (LY16F010013), The Key Science and Technology Innovation Team Foundation of Zhejiang Province (2013TD03), The National Natural Science Foundation of China (61401130)

摘要

摘要: 為了提高MLC NAND Flash的抗誤碼性能，該文提出一種基于優(yōu)化縮短極化碼的MLC NAND Flash差錯控制方法。優(yōu)化縮短極化碼通過優(yōu)化刪減圖樣得到，首先通過比特翻轉重排序的方式得到基本刪減圖樣，進而選擇具有更低信道容量的凍結比特組成優(yōu)化刪減圖樣，使得到的刪減比特全為凍結比特，可以顯著提高刪減算法的糾錯性能。同時，根據(jù)MLC單元錯誤的不對稱性，采用碼率自適應的碼字對FLASH中MSB和LSB進行不等錯誤保護。仿真結果表明：當誤幀率為10-3時，優(yōu)化縮短極化碼較相同碼長的LDPC碼和基本縮短極化碼分別約有 3.72 ~5.89 dB和1.47~3.49 dB增益；相比基于同一碼率的優(yōu)化縮短極化碼方案，不等錯誤保護的差錯控制方案獲得約0.25 dB增益。
- 極化碼 /
- 多層單元 /
- NAND Flash /
- 縮短碼 /
- 不等錯誤保護
Abstract: In order to improve the BER performance of MLC NAND Flash, this paper presents a shortened polarization-based optimized codes for MLC NAND Flash. Optimized shortened codes are obtained by optimizing shortened pattern. Firstly, basic shortened pattern is obtained by bit reversal reordering, and then the freeze bits are selected with a lower channel capacity to constitute optimized shortened pattern, the resulting punctered bits are all frozen bits, this method can significantly improve the error correction performance. Meanwhile, according to the error asymmetry of MLC unit, unequal error protection is used for the LSB and MSB. Simulation results show that the performance of the optimized shortened codes is better than LDPC and basic shortened polar code about 3.72~5.89 dB and 1.47~3.49 dB gain at the frame error rate of 10-3; compared to the same rate based optimized shortened codes, the new ECC program obtains gain about 0.25 dB .
- Polar code /
- Multi Level Cell (MLC) /
- NAND Flash /
- Shortened codes /
- Unequal Error Protection (UEP)

HTML全文

參考文獻(15)

ASLAM C A, GUAN Y L, and CAI K. Dynamic write-level and read-level signal design for MLC NAND flash memory[C]. 2014 9th International Symposium on Communication Systems, Networks Digital Signal Processing (CSNDSP), Manchester, 2014: 336-341. doi: 10.1109/CSNDSP.2014. 6923850.

SUN H, ZHAO W, LU M, et al. Exploiting intracell bit-error characteristics to improve min-sum LDPC decoding for MLC NAND flash-based storage in mobile device[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8): 2654-2664. doi: 10.1109/TVLSI.2016.2535224.

ASLAM C A, YONG L G, and CAI K. Optimal read and write signal design for multi-level-cell NAND flash memory[J]. IEEE Transactions on Communications, 2016, 64(4): 1613-1623. doi: 10.1109/TCOMM.2016.2533498.

HO Kinchu, CHEN Chihlung, and CHANG Hsiechia. A 520k (18900, 17010) array dispersion LDPC decoder architectures for NAND flash memory[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(4): 1293-1304. doi: 10.1109/TVLSI.2015.2464092.

KIM Daesung and HA Jeongseok. Serial quasi-primitive BC- BCH codes for NAND flash memories[C]. 2016 IEEE International Conference on Communications (ICC), Beijing, 2016: 1-6. doi: 10.1109/ICC.2016.7510725.

ARIKAN E. Channel polarization: A method for constructing capacity-achieving codes for symmetric binary- input memory less channels[J]. IEEE Transactions on Information Theory, 2009, 55(7): 3051-3073. doi: 10.1109/ TIT.2009. 2021379.

ESLAMI A and PISHRO N. A practical approach to polar codes[C]. 2011 IEEE International Symposium on Information Theory Proceedings (ISIT), St. Petersburg, 2011: 16-20. doi: 10.1109/ISIT.2011.6033837.

SHIN D M, LIM S C, and YANG K. Design of length- compatible polar codes based on the reduction of polarizing matrices[J]. IEEE Transactions on Communications, 2013, 61(7): 2593-2599. doi: 10.1109/TCOMM.2013.052013. 120543.

LI Y, ALHUSSIEN H, HARATSCH E F, et al. A study of polar codes for MLC NAND flash memories[C]. 2015 International Conference on Computing, Networking and Communications (ICNC), Garden Grove, CA, 2015: 608-612. doi: 10. 1109/ICCNC.2015.7069414.

LIU Y, LIU Huaida, JIN Pingui, et al. An adaptive ECC scheme for dynamic protection of NAND flash memories[C]. 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), South Brisbane, QLD, 2015: 1052-1055. doi: 10.1109/ICASSP.2015.7178130.

NIU K, CHEN K, and LIN J R. Beyond turbo codes: Rate- compatible punctured polar codes[C]. 2013 IEEE International Conference on Communications (ICC), Budapest, 2013: 3423-3427. doi: 10.1109/ICC.2013.6655078.

TARANALLI V, UCHIKAWA H, and SIEGEL P H. Channel models for multi-level cell flash memories based on empirical error analysis[J]. IEEE Transactions on Communications, 2016, 64(8): 3169-3181. doi: 10.1109/TCOMM.2016.2584602.

LIU Yumin, LIU Huaiting, CHEN Minghan, et al. Byte- reconfigurable LDPC codec design with application to high- performance ECC of NAND flash memory systems[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015, 62(7): 1794-1804. doi: 10.1109/TCSI.2015.2423798.

MACKAY J C. Good error-correcting codes based on very sparse matrices[J]. IEEE Transactions on Information Theory, 1999, 45(2): 399-431. doi: 10.1109/18.748992.

TAI I and VARDY A. How to construct polar codes[J]. IEEE Transactions on Information Theory, 2013, 59(10): 6562-6582. doi: 10.1109/TIT.2013.2272694.

施引文獻

資源附件(0)

訪問統(tǒng)計