面向密碼流體系結(jié)構(gòu)的超長指令字可重構(gòu)研究
doi: 10.11999/JEIT160213 cstr: 32379.14.JEIT160213
基金項目:
國家863計劃項目(2009AA012201)，國家自然科學(xué)基金(61302107)
Research of Reconfigurable Very Large Instruction Word on Cipher Stream Architecture
Funds:
The National 863 Project of China (2009AA 012201), The National Natural Science Foundation of China (61302107)
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摘要: 可重構(gòu)密碼流體系結(jié)構(gòu)是一種面向密碼運算的新型體系結(jié)構(gòu)，但存在著超長指令字(VLIW)代碼稀疏和Kernel體積過大的問題。該文以可重構(gòu)密碼流處理架構(gòu)S-RCCPA為研究平臺，通過大量密碼算法在S-RCCPA架構(gòu)上的適配分析，提出了VLIW可重構(gòu)技術(shù)，并設(shè)計了Kernel級指令集、VLIW可重構(gòu)算法及指令可重構(gòu)單元。實驗證明，該技術(shù)能夠有效提高VLIW的指令密度，同時降低了VLIW的指令寬度，使得整個Kernel體積減小了約33.3%，并將微碼存儲器的容量由96 kB降為64 kB，有效降低芯片整體面積和系統(tǒng)功耗。Abstract: Reconfigurable cipher stream architecture is a newly proposed architecture for cipher processing, but poor Very Large Instruction Word (VLIW) code density and huge Kernel level code cubage are always serious problems on this architecture. Through analyzing the characteristics of a series of cryptographic algorithms on Stream based Reconfiguable Clustered block Cipher Processing Array (S-RCCPA) architecture, a reconfigurable VLIW dynamically technology is proposed, and the corresponding Kernel level instruction set and hardware circuit structure are designed. The experiments demonstrate that this technology can reduce VLIW width, thus improve the instruction density of VLIW effectively. Meanwhile, it can reduce about 33% of the Kernel volume, and depress the microcode store capacity from 96 kB to 64 kB. Thus it can also reduce the whole area and power consumption of chip respectively.
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陳韜, 羅興國, 李校南, 等. 一種基于流處理框架的可重構(gòu)分簇式分組密碼處理結(jié)構(gòu)模型[J]. 電子與信息學(xué)報, 2014, 36(12): 3027-3034. doi: 10.3724/SP.J.1146.2014.00023. CHEN Tao, LUO Xingguo, LI Xiaonan, et al. An architecture of stream based reconfigurable clustered block cipher processing array[J]. Journal of Electronics Information Technology, 2014, 36(12): 3027-3034. doi: 10.3724/SP.J.1146. 2014.00023. LEE K Y, KYUNG G, PARK T R, et al. A design of a GP-GPU based stream processor for an image processing[C]. IEEE International Conference on Telecommunications Signal Processing, Prague, Czech Republic, 2015: 535-539. CHENG Tengyuan, CHEN Tsunghuang, CHEN J C, et al. Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders[C]. IEEE International SoC Design Conference, Incheon, South Korea, 2010: 95-98. KRIMER E, PAWLOWSKI R, EREZ M, et al. Synctium: A near-threshold stream processor for energy-constrained parallel applications[J]. IEEE Computer Architecture Letters, 2010, 9(1): 21-24. doi: 10.1109/L-CA.2010.5. 李校南, 王雪瑞, 戴紫彬, 等. 可重構(gòu)分簇式分組密碼處理架構(gòu)[J]. 計算機應(yīng)用與軟件, 2014, 31(1): 315-318. doi: 10.3969 /j.issn.1000-386x.2014.01.085. LI Xiaonan, WANG Xuerui, DAI Zibin, et al. Reconfigurable clustered block cipher processing architecture[J]. Computer Applications and Software, 2014, 31(1): 315-318. doi: 10.3969 /j.issn.1000-386x.2014.01.085. HUANG Wei, HAN Jun, WANG Shuai, et al. A low- complexity heterogeneous multi-core platform for security SoC[C]. IEEE Asian Solid-State Circuits Conference, Beijing, China, 2010: 126-129. WANG Bo and LIU Leibo. A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing [C]. IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, 2015: 1182-1185. SAYILAR G and CHIOU D. Cryptoraptor: high throughput reconfigurable cryptographic processor[C]. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, 2014: 155-161. 管茂林, 何義, 楊乾明, 等. 流體系結(jié)構(gòu)指令存儲器優(yōu)化設(shè)計研究[J]. 電子學(xué)報, 2012, 40(7): 1379-1385. doi: 10.3969/ j.issn.0372-2112.2012.07.016. GUAN Maolin, HE Yi, YANG Qianming, et al. Optimized design research of instruction memory for stream architecture[J]. Acta Electronica Sinica, 2012, 40(7): 1379-1385. doi: 10.3969/j.issn.0372-2112.2012.07.016. HELKALA J, VIITANEN T, KULTALA H, et al. Variable length instruction compression on transport triggered architectures[C]. IEEE International Conference on Embedded Computer Systems: Architectures, Modeling Simulation, Samos Island, Greece, 2014: 149-155. JIN T, AHN M, YOO D, et al. NOP compression scheme for high speed DSPs based on VLIW architecture[C]. IEEE International Conference on Consumer Electronics, Las Vegas, Nevada, USA, 2014: 304-305. HE Yi, GUAN Maolin, ZHANG Chunyuan, et al. Fully distributed on-chip intruction memory design for stream architecture based on field-divided VLIW compression[C]. IEEE 14th International Conference on High Performance Computing and Communications, Liverpool, United Kingdom, 2012: 25-32. CHUNG Mookyoung, KIM Junkyoung, CHO Yeongon, et al. Adaptive compression for instruction code of coarse grained reconfigurable architectures[C]. IEEE International Conference on Field-programmable Technology, Kyoto, Japan, 2013: 394-397. 李勇, 王志英, 趙學(xué)秘, 等. 配置流驅(qū)動計算體系結(jié)構(gòu)指導(dǎo)下的ASIP設(shè)計[J]. 計算機研究與發(fā)展, 2007, 44(4): 714-721. LI Yong, WANG Zhiying, ZHAO Xuemi, et al. Design of application specific instruction-set processors directed by configuration stream driven computing architecture[J]. Journal of Computer Research and Development, 2007, 44(4): 714-721. BUCHOLC K, CHMIEL K, GROCHOLEWSKA C A, et al. PP-2 block cipher[C]. International Conference on Emerging Security Information, Systems and Technologies, Barcelona, Spain, 2013: 162-168. -
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