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高效低功耗低并行度LDPC編碼方法

燕威,  薛長斌

燕威, 薛長斌. 高效低功耗低并行度LDPC編碼方法[J]. 電子與信息學(xué)報(bào), 2016, 38(9): 2268-2273. doi: 10.11999/JEIT151362
引用本文: 燕威, 薛長斌. 高效低功耗低并行度LDPC編碼方法[J]. 電子與信息學(xué)報(bào), 2016, 38(9): 2268-2273. doi: 10.11999/JEIT151362
YAN Wei, XUE Changbin. An Efficient LDPC Encoder Scheme with Low-power Low-parallel[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2268-2273. doi: 10.11999/JEIT151362
Citation: YAN Wei, XUE Changbin. An Efficient LDPC Encoder Scheme with Low-power Low-parallel[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2268-2273. doi: 10.11999/JEIT151362

高效低功耗低并行度LDPC編碼方法

doi: 10.11999/JEIT151362 cstr: 32379.14.JEIT151362

An Efficient LDPC Encoder Scheme with Low-power Low-parallel

  • 摘要: 低密度奇偶校驗(yàn)碼(LDPC)是最接近香農(nóng)極限的糾錯碼之一，具有優(yōu)良的性能且被國際通信標(biāo)準(zhǔn)組織廣泛采納為信道編碼。CCSDS推薦使用LDPC碼作為近地空間和深空探測的信道編碼方案。該文提出高效，低功耗，低并行度的LDPC編碼方法。該方法通過采用插0和改變循環(huán)矩陣的結(jié)構(gòu)實(shí)現(xiàn)了對CCSDS標(biāo)準(zhǔn)中推薦的校驗(yàn)矩陣子矩陣大小為奇數(shù)的LDPC碼的低并行度編碼。通過分析編碼過程，提出了只對輸入信息中的1有效信息位進(jìn)行編碼的方案，減少了編碼中移位寄存器的移位次數(shù)，大幅度地降低了編碼器功耗。文中采用FPGA實(shí)現(xiàn)了(8176, 7154)78LDPC碼的編碼器，結(jié)果顯示在硬件開銷略有增加的情況下，編碼功耗大幅度下降，編碼速率接近低并行度編碼方案。
    Abstract: Low-density parity-check code is the one of error-correction codes most approaching Shannon limit, which is adopted as a standard for channel coding by many international communication standard organizations. CCSDS recommends LDPC as channel coding scheme in near earth space and deep space communication. An efficient LDPC coding scheme with low power and low parallel is presented in this paper. By filling 0 and changing the cyclic-matrix structure, the proposed scheme implements a low parallel coding for the LDPC, which is recommended by CCSDS, and of which the size of submatrix of check matrices is odd. By analyzing the coding process, the valid bit 1 among input information bits is coded only, and it decreases obviously the code power. The encoder architecture for 7/8 LDPC is implemented in FPGA. The result shows that encoder achieves a high encoding speed approaching low parallel encoder scheme and a much lower encoding power while increases few hardware overhead.
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出版歷程
  • 收稿日期:  2015-12-03
  • 修回日期:  2016-05-10
  • 刊出日期:  2016-09-19

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