基于與非錐的新型FPGA邏輯簇互連結(jié)構(gòu)研究
doi: 10.11999/JEIT150249 cstr: 32379.14.JEIT150249
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2.
(中國科學(xué)院電子學(xué)研究所 北京 100190) ②(中國科學(xué)院大學(xué) 北京 100049)
基金項(xiàng)目:
國家自然科學(xué)基金(61271149)
Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster
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2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
Funds:
The National Natural Science Foundation of China (61271149)
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摘要: 該文針對(duì)新型FPGA可編程邏輯單元與非錐(And-Inverter Cone, AIC)的結(jié)構(gòu)特性，提出一系列方案以得到優(yōu)化的邏輯簇互連結(jié)構(gòu)，包括：移除輸出級(jí)交叉矩陣，單級(jí)反相交叉矩陣，低負(fù)載電路優(yōu)化，將反饋和輸出選擇功能分開，限制AIC輸出級(jí)數(shù)的基礎(chǔ)上移除中間級(jí)交叉矩陣，與LUT架構(gòu)進(jìn)行混合等。通過大量的實(shí)驗(yàn)，得出針對(duì)面積延時(shí)積最優(yōu)的AIC簇互連結(jié)構(gòu)，與Altera公司的FPGA芯片Stratix-IV結(jié)構(gòu)相比，該結(jié)構(gòu)邏輯功能簇本身面積減小9.06%, MCNC應(yīng)用電路集在基于優(yōu)化的AIC FPGA架構(gòu)上實(shí)現(xiàn)的平均面積延時(shí)積減小40.82%, VTR應(yīng)用電路集平均面積延時(shí)積減小17.38%；與原有的AIC結(jié)構(gòu)相比，簇面積減小23.16%, MCNC應(yīng)用電路集平均面積延時(shí)減小27.15%, VTR應(yīng)用電路集平均面積延時(shí)積減小15.26%。
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關(guān)鍵詞:
- 與非錐(AIC) /
- AIC簇 /
- 單級(jí)反相交叉矩陣 /
- 簇互連結(jié)構(gòu)
Abstract: With deep understanding of the characteristics of And-Inverter Cone (AIC), an alternative logic element for FPGA, a series of improvements are proposed to get an optimized interconnect architecture inside the logic cluster. The enhancements include removing the output crossbar, adopting Inverter-Suffixed Crossbar (ISC), optimizing the low load circuit path, dividing the feedback and output function, restricting the output level of AIC and removing the middle crossbar, mixing with the LUT element. An optimized architecture is derived through amounts of experiments. Compared to Stratix IV, Altera, the area of cluster is reduced by 9.06%.Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 40.82%; the average area-delay product of VTR benchmarks is reduced by 17.38%. Compared to the original AIC-based FPGA architecture, the area of AIC cluster is reduced by 23.16%. Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 27.15%; the average area-delay product of VTR benchmarks are reduced by 15.26%. -
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