基于粗粒度可重構(gòu)陣列結(jié)構(gòu)的多標(biāo)準離散余弦變換設(shè)計
doi: 10.11999/JEIT140104 cstr: 32379.14.JEIT140104
基金項目:
國家自然科學(xué)基金(61204045, 61271149)和中國科學(xué)院、國家外國專家局創(chuàng)新團隊國際合作伙伴計劃資助課題
Design of Multi-standard Discrete Cosine Transform Based on Coarse-grained Reconfigurable Array
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摘要: 在視頻信號的編解碼流程中，離散余弦變換(DCT)是一個至關(guān)重要的環(huán)節(jié)，其決定了視頻壓縮的質(zhì)量和效率。針對88尺寸的2維離散余弦變換，該文提出一種基于粗粒度可重構(gòu)陣列結(jié)構(gòu)(Coarse-Grained Reconfigurable Array, CGRA)的硬件電路結(jié)構(gòu)。利用粗粒度可重構(gòu)陣列的可重配置的特性，實現(xiàn)在單一平臺支持多個視頻壓縮編碼標(biāo)準的88 2維離散余弦變換。實驗結(jié)果顯示，這種結(jié)構(gòu)每個時鐘周期可以并行處理8個像素，吞吐率最高可達1.157109像素/s。與已有結(jié)構(gòu)相比，設(shè)計效率和功耗效率最高可分別提升4.33倍和12.3倍，并能夠以最高30幀/s的幀率解碼尺寸為40962048，格式為4:2:0的視頻序列。
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關(guān)鍵詞:
- 粗粒度可重構(gòu)陣列 /
- 視頻壓縮 /
- 離散余弦變換 /
- 功耗效率
Abstract: Discrete Cosine Transform (DCT) plays an important role in the codec process of video signals, and has a significant influence on the compression efficiency and quality. In this paper, a Coarse-Grained Reconfigurable Array (CGRA) based hardware architecture is proposed for 8-point 2D DCT. Through the reconfiguration of coarse-grained reconfigurable array, the proposed architecture is capable of supporting 88 2D discrete cosine transform of the multiple video compression coding standards in a single platform. The experimental results show that the proposed architecture is able to parallel process 8 pixels in a cycle, and the throughput achieves up to 1.157109 pixels per second. The design efficiency and power efficiency is about 4.33 times and 12.3 times higher than existing works respectively. Moreover, the proposed architecture can support real-time decoding of 40962048 at 30 fps (4:2:0) video sequences. -
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