基于FPGA的數(shù)字高清晰度電視視頻解碼器的設(shè)計和實現(xiàn)
THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER
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摘要: 本文介紹了一個能實時解碼基于MPEG-2的高清晰度電視(HDTV)編碼流的視頻解碼器的設(shè)計方案及其實現(xiàn)。在設(shè)計中采用大量FPGA以及能實現(xiàn)高速處理的并行處理技術(shù)和流水線工作方式,并研究了由并行處理而導(dǎo)致的運動補償越界等特殊問題的解決途徑。論文闡明了解碼器的總體結(jié)構(gòu)和各主要電路的組成以及整個解碼過程的具體實現(xiàn)。Abstract: This paper presents the scheme and its implementation of a video decoder, which can complete real-time decoding the MPEG-2 based coded bit stream. This scheme adopts the parallel processing technique, the operation in pipe line and a large quantity of FPGA. The approach for the motion compensation crossing the border, which is caused by parallel processing, is studied. The architecture of the decoder, the formation of main circuits and the realization of decoding procedue are described.
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ISO/IEC IS 13818. Generic Coding of Moving Picture and Associated Audio. Nov. 1994.[2]周萍.數(shù)字高清晰度電視視頻解碼器的研究:[博士論文],天津:天津大學(xué),1996年6月.[3]Xilinx. Inc. The Programmable Logic Data Book. 1994.[4]Grand Alliance HDTV System Specification. Version 1.0. Apr. 1994.[5]Lei S M, Sun M T. An entropy coding system for digital HDTV application. IEEE Trans. on CAS VT, 1991, 1(1): 147-155. -
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