Round robin調(diào)度算法在FPGA中的實(shí)現(xiàn)
The FPGA implementation of the round robin scheduling algorithms
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摘要: Round robin調(diào)度算法是一個(gè)在許多方面有著廣泛應(yīng)用的經(jīng)典調(diào)度算法。該文在考慮了FPGA的結(jié)構(gòu)特點(diǎn)和實(shí)際系統(tǒng)需求后，利用桶式移位器和分段式優(yōu)先級(jí)編碼器，在FPGA中實(shí)現(xiàn)了Round robin調(diào)度算法，并對(duì)實(shí)現(xiàn)方法的面積和性能進(jìn)行了討論。系統(tǒng)測(cè)試結(jié)果表明該算法實(shí)現(xiàn)是高效的，滿足了系統(tǒng)的需求，在實(shí)際系統(tǒng)中運(yùn)行狀況良好。
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關(guān)鍵詞:
- Round robin;調(diào)度算法;FPGA
Abstract: Round robin scheduling algorithm is a classic scheduling algorithm with many ap-plications. An FPGA implementation by using barrel shifter and pipelined priority encoder is presented in this paper with considering the FPGA structure characteristic and systems requirement. And the performance and resource consumption of the implementation are dis-cussed. The test result shows that the implementation of the algorithm is effective and fit for the FPGA structure. The system with the implementation of algorithm runs very well. -
M.G.H. Katevenis, Fast switching and fair control of congested flow in broadband networks,IEEE on Selected Areas Comm., 1987, SAC-5(8), 1315-1326.[2]The Programmable Logic Data Book 2000, Xilinx Incorporation, 2000, Section 3.[3]夏宇聞,復(fù)雜數(shù)字電路與系統(tǒng)的Verilog HDL設(shè)計(jì)技術(shù),北京,北京航空航天大學(xué)出版社,1998,第二章,第四章. -
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