集成電路參數(shù)中心值和容差的耦合設(shè)計(jì)方法
The Coupling Technique for ICs Centering Design and Tolerance Optimization
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摘要: 基于對(duì)集成電路參數(shù)成品率中心值設(shè)計(jì)和容差分配的研究,該文提出了一種參數(shù)成品率中心值設(shè)計(jì)和容差分配耦合求解最優(yōu)設(shè)計(jì)值的算法。該算法不需要設(shè)計(jì)者對(duì)電路或工藝的物理結(jié)構(gòu)非常熟悉,從任意初始設(shè)計(jì)值和任意大小的容差,算法均可收斂到可接受域中的最優(yōu)設(shè)計(jì)值。另外,根據(jù)工藝線的容差,算法可確定集成電路的最優(yōu)參數(shù)成品率,也可根據(jù)實(shí)際要求選擇適當(dāng)容差的工藝線,以降低生產(chǎn)成本、提高效益。最后用實(shí)例證明了該算法的可行性和實(shí)用性,得到了滿意的結(jié)果。Abstract: A coupling technique is proposed based on parametric yields centering design and tolerance optimization. The technique is convergence to the optimal normal values from given initial design variable and tolerance with little knowledge of circuit, device or technology. In the optimal value, the maximum yield can be obtained according to technology condition while proper technology conditions can be chosen according to practical requirements. Finally, the feasibility and utility of the method are demonstrated satisfactorily by numerical and practical examples.
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