一種級(jí)聯(lián)結(jié)構(gòu)的高階全數(shù)字鎖相環(huán)
A HIGH ORDER ALL DIGITAL PHASE LOCKED LOOP WITH TANDEM STRUCTURE
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摘要: 本文給出了一種高階全數(shù)字鎖相環(huán)的級(jí)聯(lián)結(jié)構(gòu)形式,它通過(guò)結(jié)構(gòu)簡(jiǎn)單的全數(shù)字一階環(huán)的級(jí)聯(lián)來(lái)實(shí)現(xiàn)高階環(huán)路。它避免了通常的高階鎖相環(huán)中較復(fù)雜的數(shù)字濾波器,實(shí)現(xiàn)簡(jiǎn)單,易于集成。本文介紹了級(jí)聯(lián)全數(shù)字二階環(huán)的原理和實(shí)現(xiàn),對(duì)其性能進(jìn)行了理論分析和計(jì)算機(jī)仿真,最后給出一個(gè)應(yīng)用實(shí)例。
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關(guān)鍵詞:
- 全數(shù)字鎖相環(huán); 指針泄漏; 抖動(dòng)
Abstract: A high order all digital phase locked loop with tandem structure is presented. A 2-order all digital PLL is implemented and its performance is verified by simulation. An example is given for SDH 2048Kb/s tributary recovery. Its performances are simulated and compared with the theoretical analysis. -
Loau Chii-Min, Wu Ji-Tsu. PHDPLL for SONET desynchronzer. GLOBECOM91, Phoenix, USA: 1991, 402-405.[2]ITU-T Recommendation G.783(Draft), Characteristics of synchronous digital hierarchy(SDH)[3]equipment functional blocks, 12.04.1997.[4]ITU-T Recommendation 6.823, The control of jitter and wander within digital networks which are based on the SDH, 1992.[5]張厥盛, 鄭繼禹, 萬(wàn)心平. 鎖相技術(shù)西安:西安電子科技大學(xué)出版社, 1994，第七章, 第一節(jié).[6]Hiknet Sari, et al. Cancellation of pointer adjustment jitter in SDH network. IEEE Trans. on Communications, 1994, COM-42(12): 3200-3207.[7]Kusyk R G, et al. Analysis of techniques for the reduction of jitter caused by SONET pointer adjustments. IEEE Trans. on Communications, 1994, COM-42(2/3/4): 2036-2050.[8]Transwitch Data Sheet, ADMA-El 2Mbit/s to TU-12 asynchronous mapper/desynchronizer, TXC-04002-MB, Ed.3A, August 1995. -
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