注硅不摻雜半絕緣GaAs中的深能級(jí)缺陷
DEEP LEVEL DEFECTS IN Si-IMPLANTED LEC UNDOPED SI-GaAs
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摘要: 用DLTS法對(duì)經(jīng)兩步快速熱退火(RTA)后的注硅不摻雜SI-GaAs中的缺陷進(jìn)行了研究。確定了激活層中存在著兩個(gè)電子陷阱組(以主能級(jí)ET1、ET2標(biāo)記)及其電學(xué)參數(shù)的深度分布。在體內(nèi),ET1=Ec0.53eV,n=2.310-16cm2;ET2=Ec0.81eV,m=9.710-13cm2;密度典型值為NT1=8.01016cm-3,NT2=3.81016cm-3;表面附近,ET1=Ec0.45eV,NT1=1.91016cm-3;ET2=Ec0.71eV,NT2=1.21016cm-3,分別以[AsiVAs,AsGa]和[VAsAsiVGaAsGa]等作為ET1和ET2的缺陷構(gòu)型解釋了它們?cè)赗TA過程中的行為。
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關(guān)鍵詞:
- 注硅砷化鎵; 快速熱退火; 離子注入; 深能級(jí)
Abstract: DLTS technique has becn used to investigate (4 1012cm-2/30keV+5 1012cm-2/ 130keV)Si implanted LEC undoped SI-GaAs annealed by tow-step rapid thermal annealing (RTA) (970℃/9s +750℃/12s). Two electron traps ET1(Ec- 0.53 eV, 2.3 10-16cm2) and ET2(Ec-0.81eV, 9.710-13cm2) are detected. Furthermore, the noticeable variations of trap s concentration and energy level in the forbidden gap with the depth profile of defects induced by ion implantation and RTA processes have been observed, The [Asi VAsAsGa] and [VAsAsiVGaAsGa] are proposed as the possible atomic configurations of ET1,and ET2 respectively to explain their RTA behavior. -
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