高清晰度電視視頻解碼器系統(tǒng)控制的設(shè)計(jì)與實(shí)現(xiàn)
Design and implementation of system control for the HDTV video decoder
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摘要: 該文提出了一種高清晰度電視(HDTV)視頻解碼器系統(tǒng)控制的設(shè)計(jì)方案,并對(duì)其工作原理進(jìn)行了闡述。該方案采用FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列)技術(shù)實(shí)現(xiàn),具有設(shè)計(jì)靈活,方便的特點(diǎn),經(jīng)整機(jī)聯(lián)試系統(tǒng)控制工作穩(wěn)定、可靠,保障了正常的解碼和顯示。
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關(guān)鍵詞:
- 高清晰度電視（HDTV）; 系統(tǒng)控制; MPEG-2; FPGA
Abstract: This paper presents the design and implementation of system control for HDTV video decoder. The principle of the system control is described in detail too. FPGA is adopted for its programmable and reconfigurable features. The system control works perfectly and steadily which ensures the perfect work of decoder and display buffer. -
ISO/IEC 13818-1 Generic Coding of Moving Pictures and Associated Audio Information: System,Jan. 20, 1995. ［2］SO/IEC 13818-2 Generic Coding of Moving Pictures and Associated Audio Information: Video,Jan. 20, 1995. ［3］ATSC: ATSC Digital Television Standard, Oct. 4, 1995.[2]ATSC: Guide to the Use of the ATSC Digital Television Standard, Oct. 4, 1995.[3]K. Kawahara, H. Yamauchi, S. Okada, A single chip MPEG1 decoder, IEEE Trans. on Consumer Electronics, 1995, 41(3), 707-715.[4]Aldo Cugnini, Richard Shen, MPEG-2 video decoder for the digital HDTV grand allance system,IEEE Trans. on Consumer Electronics, 1995, 41(3), 748-752. -
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