PCI總線多用戶數(shù)據(jù)緩沖區(qū)管理器的實(shí)現(xiàn)
Implementation of PCI Bus Multi-user Data Buffer Manager
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摘要: 分析了一種PCI總線上支持多個(gè)用戶的數(shù)據(jù)緩沖區(qū)管理器電路所采用的電路結(jié)構(gòu),給出了關(guān)鍵點(diǎn)的仿真波形.從理論上分析了用戶的緩沖區(qū)分配原則、端口總線帶寬、用戶最大服務(wù)等待時(shí)間和最小緩沖區(qū)數(shù)量等工作參數(shù).給出了多用戶緩沖區(qū)管理器中所需要最小存儲(chǔ)區(qū)的計(jì)算方法.以分析為基礎(chǔ),采用XILINX的XCV600EPQ240實(shí)現(xiàn)了128用戶緩沖區(qū)管理器電路,并在實(shí)際系統(tǒng)中進(jìn)行了測(cè)試和驗(yàn)證.Abstract: The circuit structure of a kind of PCI bus multi-user data Buffer Manager (BM) is analyzed in this paper, and typical simulating waveform is presented. The method to allocate the data buffers, port bandwidth, maximum user waiting time and minimum user buffer requirements are analyzed theoretically. The expression to calculate the minimum memory needed in the BM is given. Based on the analysis, a 128-user buffer manager is realized with XILINX XCV600EPQ240 and verified in application systems.
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