一種大頻偏和低信噪比條件下的全數字鎖相環(huán)設計
The Design of DPLL for Low SNR Signals with Large Frequency Offset
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摘要: 全數字鎖相環(huán)設計是相干解調全數字接收機載波同步和位同步的關鍵技術,而大頻偏和低信噪比分別從兩個方面增加了環(huán)路設計的難度.該文在此背景下,以捕獲時間和跟蹤性能為指標,從模擬環(huán)路分析出發(fā),給出一種適用于大頻偏和低信噪比條件的全數字鎖相環(huán)設計.Abstract: The digital phase-locked loops design is a key technology for carrier and bit synchronization in coherent demodulation digital receiver. Large frequency offset and low SNR add more difficulties of the loop design from two different ways. Based on this condition, aim at fast acquisition and tracking, a method of digital loop parameter algorithm is proposed in this paper and some useful conclusions are given.
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張厥盛,鄭繼禹,萬心平.鎖相技術.西安:西安電子科技大學出版社,1992:5-6,20-23.[2]John G. Proakis. Digital Communications. 3rd Ed., New York: Mc Graw-Hill, Inc., 1996: chapter 6.[3]Vilnrotter V, Gray A Lee. Carrier synchronization for low signal-tonoise ratio binary phase-shift-keyed modulated signals. TMO Progress Report: 42 - 139.[4]Ascheid Gerd, Meyr Heinrich. Cycle slips in phase-lock loops: a tutorial study. IEEE Trans. on Comm., 1982, COM-30(10): 2228-2241.[5]Viterbi A J. principles of Coherent Communications. New York:McGraw-Hill, 1966, chaper 2.[6]Jaffe R, Rechtin E. Design and performance of false-lock loops capable of near-optimum performance over a wide range of input signal and noise levels. IRE Trans. on IT, 1965, IT-1(3): 66-72.[7]Bong-Young Chung, Charles Chien, Henry Samueli. Performance analysis of an all-digital BPSK direct sequence spread-spectrum IF receiver architecture[J].IEEE J. on Selected 4reas in Communications.1993, 11(7):1096-[8]Ali I, Al-Dhahir N, Hershey J E. Dopplercharacterization for LEO satellites[J].IEEE Trans. on Communications.1998, 46(3):309- -
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