時序電路的狀態(tài)驗證研究與設(shè)計
VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS
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摘要: 采用二元判定圖(BDD)作為工具來描述時序電路是非常有意義和有效的.本文通過對BDD的簡化達(dá)到對狀態(tài)變換圖(STG)輸入、路徑和狀態(tài)的壓縮,從而提高狀態(tài)遍歷的效率,另外根據(jù)電路的特點(diǎn),提出狀態(tài)沖突和不相交分解的啟發(fā)技術(shù)以有效地完成驗證.
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關(guān)鍵詞:
- 二元判定圖; 節(jié)點(diǎn); 壓縮; 狀態(tài)變換圖
Abstract: It is very effective that use BDD to describe the synchronous circuits. This paper has proposed the reducing way for BDD in order to collapse the number of inputs, routes and states. Based on the features of circuit, several heuristic methods that speed up verification are presented. -
Odawara G.[J].et al. A logic verifier based on Boolean comparison, DA8.1986,:-. A logic verifier based on Boolean comparison, DA' target='_blank'>[2]Bose S.[J].Fisher A L. Automatic verification of synchronous circuits using symbolic logic simulation and temporal logic, IFIP9.1990,:-Touati H J.[J].et al.Implicit state enumeration of finite state machine using BDDs, ICCAD9.1990,:-.Implicit state enumeration of finite state machine using BDD' target='_blank'> -
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