一種低延遲的3維高效視頻編碼中深度建模模式編碼器
doi: 10.11999/JEIT180798 cstr: 32379.14.JEIT180798
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合肥工業(yè)大學電子科學與應用物理學院?合肥?230009
基金項目: 國家自然科學基金(61474036),教育部IC設計網(wǎng)上合作研究中心項目(JSGG20170413153845042)
A Low-latency Depth Modelling Mode-1 Encoder in 3D-high Efficiency Video Coding Standard
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School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009, China
Funds: The National Natural Science Foundation of China(61474036), The Project of IC Design Web-cooperation Research Center of MOE(JSGG20170413153845042)
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摘要: 為了更好地對3D視頻中深度圖進行編碼,該文將3維高效視頻編碼(3D-HEVC)標準新引入了深度建模模式(DMMs),新模式在提高了編碼質量的同時改進了原有算法的復雜度。在設計DMM-1編碼器電路時,傳統(tǒng)架構電路的編碼周期均較長,只能滿足較低分辨率和幀率的視頻實時編碼要求。為了進一步提高3D-HEVC中DMM-1編碼器的性能,該文對DMM-1算法架構進行了研究,針對其中楔形塊評估無數(shù)據(jù)相關性的特點,提出了一種5級流水線架構的DMM-1編碼器硬件電路,以期能夠降低一個深度塊編碼所需的編碼周期,并使用Verilog HDL進行實現(xiàn)。實驗表明:該架構與Sanchez等人(2017年)的工作相比,以電路門數(shù)增加約1568門為代價,可減少至少52.3%的編碼周期。Abstract: In order to encode better the depth maps in 3D video, the 3D-High Efficiency Video Coding (3D-HEVC) standard is introduced in Depth Modeling Modes(DMMs), which increase the quality of original algorithm while improving the encoding complexity. The traditional architecture of DMM-1 encoder circuit has a longer coding period and can only meet real-time coding requirements of lower resolution and frame rate. In order to improve the performance of DMM-1 encoder, the structure of DMM-1 algorithm is researched and a five-stage pipeline architecture of DMM-1 encoder is proposed. The pipeline architecture can reduce the coding cycles. The architecture is implemented by Verilog HDL. Experiments show that this architecture can reduce the coding cycle by at least 52.3%, at the cost of 1568 gates compared to previous work by Sanchez G. et al. (2017).
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