近閾值電壓下可容錯(cuò)的末級(jí)緩存結(jié)構(gòu)設(shè)計(jì)

劉偉; 魏志剛; 杜薇; 曹廣義; 王偉

doi:10.11999/JEIT170989

近閾值電壓下可容錯(cuò)的末級(jí)緩存結(jié)構(gòu)設(shè)計(jì)

doi: 10.11999/JEIT170989 cstr: 32379.14.JEIT170989

^①(武漢理工大學(xué)計(jì)算機(jī)科學(xué)與技術(shù)學(xué)院武漢 430070)^②(交通物聯(lián)網(wǎng)技術(shù)湖北省重點(diǎn)實(shí)驗(yàn)室武漢 430070) ^③(同濟(jì)大學(xué)計(jì)算機(jī)科學(xué)與技術(shù)系上海 200092)

基金項(xiàng)目:

國(guó)家自然科學(xué)基金(61672384)，教育部人文社科項(xiàng)目(16YJCZH014)，湖北省自然科學(xué)基金(2016CFB466)，中央高?；究蒲袠I(yè)務(wù)費(fèi)(WUT: 2016III028, 2017III028-005) ，湖北省技術(shù)創(chuàng)新專(zhuān)項(xiàng)重大項(xiàng)目(2017AAA122)

詳細(xì)信息

作者簡(jiǎn)介:
劉偉：劉偉：男，1978年生，博士，副教授，主要研究方向?yàn)榈凸南到y(tǒng)結(jié)構(gòu)、云計(jì)算與服務(wù)計(jì)算. 魏志剛：男，1993年生，碩士生，研究方向?yàn)榈凸南到y(tǒng)結(jié)構(gòu)、近閾值計(jì)算. 杜薇：女，1978年生，博士，副教授，主要研究方向?yàn)榫G色計(jì)算、云計(jì)算與服務(wù)計(jì)算. 曹廣義：男，1984年生，博士，講師，主要研究方向?yàn)樵朴?jì)算、綠色計(jì)算. 王偉：男，1979年生，博士，副教授，主要研究方向?yàn)榫G色計(jì)算、云計(jì)算.

中圖分類(lèi)號(hào): TP302.8
計(jì)量
- 文章訪問(wèn)數(shù): 1496
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- 被引次數(shù): 0
出版歷程
- 收稿日期: 2017-10-23
- 修回日期: 2018-04-03
- 刊出日期: 2018-07-19

Fault-tolerant Last Level Cache Architecture Design at Near-threshold Voltage

LIU Wei^①② WEI Zhigang^① DU Wei^①② CAO Guangyi^① WANG Wei^③

Funds:

The National Natural Science Foundation of China (61672384), The Ministry of Education of Humanities and Social Science project (16YJCZH014), The Natural Science Foundation of Hubei Province (2016CFB466), The Fundamental Research Funds for the Central Universities (WUT: 2016III028, 2017III028-005), Major Program of Technical Innovation Special Program in Hubei Province of China (2017AAA122)

摘要

摘要: 近閾值電壓技術(shù)通過(guò)降低晶體管的電源電壓來(lái)降低芯片能耗和提升能效。但是，近閾值電壓技術(shù)會(huì)在Cache中引起大量位錯(cuò)誤，嚴(yán)重影響末級(jí)緩存的功能。針對(duì)近閾值電壓下超過(guò)1%的位錯(cuò)誤率造成的Cache故障問(wèn)題，該文提出一種基于傳統(tǒng)6T SRAM單元的可容錯(cuò)的末級(jí)緩存結(jié)構(gòu)(FTLLC)。該策略對(duì)緩存條目中的錯(cuò)誤進(jìn)行了低錯(cuò)糾正和多錯(cuò)壓縮，提高了Cache中數(shù)據(jù)保存的可靠性。為了驗(yàn)證FTLLC的有效性，該文在gem5中實(shí)現(xiàn)了該結(jié)構(gòu)，并運(yùn)行了SPEC CPU2006測(cè)試集進(jìn)行仿真實(shí)驗(yàn)。結(jié)果表明，對(duì)于650 mV電壓下65 nm工藝的末級(jí)緩存，F(xiàn)TLLC與Concertina壓縮機(jī)制相比在4-Byte粒度下末級(jí)緩存可用容量增加了24.9%，性能提高了7.2%，末級(jí)緩存的訪存缺失率下降了58.2%，而面積和能耗開(kāi)銷(xiāo)僅有少量增加。
- 近閾值電壓 /
- 容錯(cuò)Cache /
- 糾錯(cuò)碼 /
- 壓縮機(jī)制
Abstract: Near-threshold voltage computing enables transistor voltage scaling to continue with Moore’s Law projection and dramatically improves power and energy efficiency. However, a great number of bit-cell errors occur in large SRAM structures, such as Last-Level Cache (LLC). A Fault-Tolerant LLC (FTLLC) design with conventional 6T SRAM cells is proposed to deal with a higher failure rate which is more than 1% at near-threshold voltage. FTLLC improves the reliability of data stored in Cache by correcting the single-error and compressing multi-errors in Cache entry. To validate the efficiency of FTLLC, FTLLC and prior works are implemented in gem5, and are simulated with SPEC CPU2006. The experiment shows that compared with Concertina at 650 mV, the performance of a 65 nm FTLLC with 4-Byte subblock size improves by 7.2% and the Cache capacity increases by 24.9%. Besides, the miss rate decreases by 58.2%, and there are little increases on area overhead and power consumption.
- Near-threshold voltage、Fault-tolerant Cache、Error correction code、Compression mechanism /

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參考文獻(xiàn)(20)

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