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可重構(gòu)非線性布爾函數(shù)利用率模型研究與硬件設(shè)計

戴紫彬,  王周闖,  李偉,  李嘉敏,  南龍梅

戴紫彬, 王周闖, 李偉, 李嘉敏, 南龍梅. 可重構(gòu)非線性布爾函數(shù)利用率模型研究與硬件設(shè)計[J]. 電子與信息學(xué)報, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
引用本文: 戴紫彬, 王周闖, 李偉, 李嘉敏, 南龍梅. 可重構(gòu)非線性布爾函數(shù)利用率模型研究與硬件設(shè)計[J]. 電子與信息學(xué)報, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733
Citation: DAI Zibin, WANG Zhouchuang, LI Wei, LI Jiamin, Nan Longmei. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. Journal of Electronics & Information Technology, 2017, 39(5): 1226-1232. doi: 10.11999/JEIT160733

可重構(gòu)非線性布爾函數(shù)利用率模型研究與硬件設(shè)計

doi: 10.11999/JEIT160733 cstr: 32379.14.JEIT160733
  • 1.

    (解放軍信息工程大學(xué) 鄭州 450001) ②(復(fù)旦大學(xué)專用集成電路與系統(tǒng)國家重點實驗室 上海 200433)

基金項目: 

國家自然科學(xué)基金(61404175)

Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function

  • 1.

    (The PLA Information Engineering University, Zhengzhou 450001, China)

  • 2.

    (State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China)

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 為解決序列密碼中非線性布爾函數(shù)(Non-Linear Boolean Function, NLBF)硬件資源利用率低的問題，該文對以查找表(Look-Up Table, LUT)為基本構(gòu)件的利用率模型進行研究，并結(jié)合適配算法的前期處理結(jié)果確定影響硬件利用率的3個基本參數(shù)(LUT大小、單元規(guī)模和輸入端口數(shù)目)；在此基礎(chǔ)上，以變量頻次為約束實現(xiàn)NLBF的映射，完成非線性運算單元的設(shè)計，單元支持多路并行處理。在SMIC 180 nm下進行邏輯綜合，并行度為32時，工作頻率達到241 MHz，吞吐率為7.71 Gb/s；對不同NLBF進行利用率評估，利用率均達到91.14%以上，并且隨著并行度增加，利用率不斷增大。
    Abstract: In order to solve the problem that the Non-Linear Boolean Function (NLBF) unit in sequence cryptogram possesses poor hardware resource utilization, the utilization model of basic component composed by Look-Up Table (LUT) is studied and three essential parameters (LUT size, cluster scale and the number of input ports) which impact hardware utilization are decided combined with the early processing results of adaption algorithm. On the basis, the mapping of NLBF limited to variable frequency is realized and the design of nonlinear computing unit is implemented, which can support multi-way parallel processing. The circuit is developed and synthesized in SMIC 180 nm. Its working frequency realizes 241 MHz and it achieves the maximum throughput of 7.71 Gb/s in parallelism of 32. The results after evaluating the utilization of various NLBFs show that all utilization can reach over 91.14% and the utilization increases continually as the parallelism increases.
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出版歷程
  • 收稿日期:  2016-07-08
  • 修回日期:  2016-12-12
  • 刊出日期:  2017-05-19

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