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超高速全并行快速傅里葉變換器

陳杰男,  費(fèi)超,  袁建生,  曾維棋,  盧浩,  胡劍浩

陳杰男, 費(fèi)超, 袁建生, 曾維棋, 盧浩, 胡劍浩. 超高速全并行快速傅里葉變換器[J]. 電子與信息學(xué)報(bào), 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036
引用本文: 陳杰男, 費(fèi)超, 袁建生, 曾維棋, 盧浩, 胡劍浩. 超高速全并行快速傅里葉變換器[J]. 電子與信息學(xué)報(bào), 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036
CHEN Jienan, FEI Chao, YUAN Jiansheng, ZENG Weiqi, LU Hao, HU Jianhao. An Ultra-high-speed Fully-parallel Fast Fourier Transform Design[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036
Citation: CHEN Jienan, FEI Chao, YUAN Jiansheng, ZENG Weiqi, LU Hao, HU Jianhao. An Ultra-high-speed Fully-parallel Fast Fourier Transform Design[J]. Journal of Electronics & Information Technology, 2016, 38(9): 2410-2414. doi: 10.11999/JEIT160036

超高速全并行快速傅里葉變換器

doi: 10.11999/JEIT160036 cstr: 32379.14.JEIT160036
基金項(xiàng)目: 

國(guó)家自然科學(xué)基金(6150010678, 61371104)

An Ultra-high-speed Fully-parallel Fast Fourier Transform Design

Funds: 

The National Natural Science Foundation of China (6150010678, 61371104)

  • 摘要: 設(shè)計(jì)和實(shí)現(xiàn)超高速快速傅里葉變換器(FFT)在雷達(dá)與未來無線通信等系統(tǒng)中具有重要意義。該文提出首個(gè)全并行架構(gòu)的FFT處理器，其避免了復(fù)雜的路由尋址以及數(shù)據(jù)訪問沖突等問題，基于較大基進(jìn)行分解降低運(yùn)算復(fù)雜度。由于旋轉(zhuǎn)因子已知和固定，大量的乘法轉(zhuǎn)化為了定系數(shù)乘法。同時(shí)由于采用了串行的計(jì)算單元，在達(dá)到全并行結(jié)構(gòu)的高速度同時(shí)硬件復(fù)雜度相對(duì)較低；所有的硬件計(jì)算單元處于滿載的條件，其硬件效率能達(dá)到100%。根據(jù)實(shí)際的實(shí)現(xiàn)結(jié)果，所提出的512點(diǎn)FFT處理器結(jié)構(gòu)能夠達(dá)到5.97倍速度面積比的提升，同時(shí)硬件開銷僅占用了Xilinx V7-980t FPGA 30%的查找表資源與9%的寄存器資源。
    Abstract: The design and implementation of ultra-high-speed FFT processor is imperative in radar system and prospective wireless communication system. In this paper, the fully-parallel-architecture FFT with bit-serial arithmetic is proposed. This method avoids the complexity of data addressing, access and routing. Based on the high-radix factorization, the multiplication number can be reduced. Out of the reason that twiddle factors are fixed in the design, constant coefficient optimization can be used in multiplications. Besides, bit-serial arithmetic cuts down the hardware cost, and makes the computation elements full-load to get a 100% efficiency. As a result, the presented 512-point FFT processer has 5.97 times gain in speed-throughput ratio while its hardware only accounts for 30% LUTs and 9% registers resource based on Xilinx V7-980t FPGA.
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  • 霍凱, 趙晶晶. OFDM新體制雷達(dá)研究現(xiàn)狀與發(fā)展趨勢(shì)[J]. 電子與信息學(xué)報(bào), 2015, 37(11): 2776-2789. doi: 10.11999/ JEIT150335.
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出版歷程
  • 收稿日期:  2016-01-13
  • 修回日期:  2016-05-30
  • 刊出日期:  2016-09-19

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