一種基于與非錐簇架構(gòu)FPGA輸入交叉互連設(shè)計(jì)優(yōu)化方法
doi: 10.11999/JEIT151216 cstr: 32379.14.JEIT151216
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2.
(中國(guó)科學(xué)院電子學(xué)研究所 北京 100190) ②(中國(guó)科學(xué)院大學(xué) 北京 100190)
基金項(xiàng)目:
國(guó)家自然科學(xué)基金(61271149)
An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA
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2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
Funds:
The National Natural Science Foundation of China (61271149)
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摘要: 該文針對(duì)與非錐(And-Inverter Cone, AIC)簇架構(gòu)FPGA開發(fā)中面臨的簇面積過大的瓶頸問題，對(duì)其輸入交叉互連設(shè)計(jì)優(yōu)化進(jìn)行深入研究，在評(píng)估優(yōu)化流程層次，首次創(chuàng)新性提出裝箱網(wǎng)表統(tǒng)計(jì)法對(duì)AIC簇輸入和反饋資源占用情況進(jìn)行分析，為設(shè)計(jì)及優(yōu)化輸入交叉互連結(jié)構(gòu)提供指導(dǎo)，以更高效獲得優(yōu)化參數(shù)。針對(duì)輸入交叉互連模塊，在結(jié)構(gòu)參數(shù)設(shè)計(jì)層次，首次提出將引腳輸入和輸出反饋連通率分離獨(dú)立設(shè)計(jì)，并通過大量的實(shí)驗(yàn)，獲得最優(yōu)連通率組合。在電路設(shè)計(jì)實(shí)現(xiàn)層次，有效利用AIC邏輯錐電路結(jié)構(gòu)特點(diǎn)，首次提出雙相輸入交叉互連電路實(shí)現(xiàn)。相比于已有的AIC簇結(jié)構(gòu)，通過該文提出的優(yōu)化方法所得的AIC簇自身面積可減小21.21%，面積制約問題得到了明顯改善。在實(shí)現(xiàn)MCNC和VTR應(yīng)用電路集時(shí)，與Altera公司的FPGA芯片Stratix IV(LUT架構(gòu))相比，采用具有該文所設(shè)計(jì)的輸入交叉互連結(jié)構(gòu)的AIC架構(gòu)FPGA，平均面積延時(shí)積分別減小了48.49%和26.29%；與傳統(tǒng)AIC架構(gòu)FPGA相比，平均面積延時(shí)積分別減小了28.48%和28.37%，顯著提升了FPGA的整體性能。
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關(guān)鍵詞:
- 與非錐(AIC); AIC簇 /
- 裝箱網(wǎng)表統(tǒng)計(jì)法 /
- 連通率 /
- 分類獨(dú)立設(shè)計(jì) /
- 雙相輸入交叉互連
Abstract: In order to break through the bottleneck of the huge cluster area in AIC (And-Inverter Cone) architecture based FPGA, the research on the optimisation of the input crossbar architecture is carried on. A post-pack netlist statistics method is creatively proposed to analyze the utilization of AIC cluster inputs and feedbacks and to guide the input crossbar design. And on the architecture parameter design level, it is firstly proposed to separately design the connective probability of the AIC cluster inputs and feedbacks. Through substantial experiments, optimum connective probability combination is derived. From the circuit implement view, dual-phases multiplexer input crossbar is presented according to the characteristics of AIC. The area of the AIC cluster, optimized through the proposed approach, achieves 21.21% smaller than the original one, the huge area problem is markedly ameliorated. When implementing the MCNC and VTR benchmarks, compared to Stratix IV, LUT based FPGA from Altera, the area-delay product of the AIC FPGA after optimisation is reduced by 48.49% and 26.29%, respectively. Compared to the original AIC-based FPGA architecture, the area-delay product is reduced by 28.48% and 28.37%, respectively. -
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