數(shù)據(jù)鎖存處理的低誤碼率編碼方法研究
doi: 10.11999/JEIT151104 cstr: 32379.14.JEIT151104
-
1.
(東南大學(xué)無(wú)錫分校 無(wú)錫 214135) ②(東南大學(xué)集成電路學(xué)院 南京 210096)
江蘇省自然科學(xué)基金(BK2012559)
Research on Low Bit Error Rate Encoding Method for Data Latch Processing
-
1.
(Wuxi Branch, Southeast University, Wuxi 214135, China)
-
2.
(Institute of Integrated Circuit, Southeast University, Nanjing 210096, China)
Natural Science Foundation of Jiangsu Province (BK2012559)
-
摘要: 對(duì)于時(shí)間信號(hào)量化后的數(shù)字編碼處理,傳統(tǒng)編碼方法高頻條件下存在高誤碼率導(dǎo)致數(shù)據(jù)量化精度退化的問(wèn)題。該文從數(shù)據(jù)誤碼根源分析入手,建立起不同狀態(tài)模式下包含鎖存和延遲失配效應(yīng)的誤碼解析分析模型,并在二進(jìn)制和格雷碼編碼方法對(duì)比的基礎(chǔ)上,分析了低誤碼率的同頻碼編碼設(shè)計(jì)方法。基于TSMC 0.35 ?m CMOS工藝,完成了采用同頻碼編碼方法的時(shí)間數(shù)字轉(zhuǎn)換器(TDC)電路及其版圖設(shè)計(jì),多項(xiàng)目晶元(MPW)芯片的測(cè)試結(jié)果表明:同頻編碼的誤碼率相比同等條件下傳統(tǒng)編碼方法的誤碼率明顯降低,并與理論分析基本吻合。
-
關(guān)鍵詞:
- 沙箱攔截 /
- 系統(tǒng)函數(shù)集 /
- 鉤子 /
- 函數(shù)注入 /
- 自動(dòng)機(jī)
Abstract: In the data processing of quantified time signal, traditional encoding method in high frequency is faced with the problem of high Bit Error Rate (BER) affecting the datas quantitative accuracy. This paper presents BER mechanism analytical model according to the analysis of the causes of bit error, which takes both data latch and delay mismatch effects of different state pattern into consideration. And the analysis of same frequency coding mode with low BER is put forward based on the comparison of the binary and Gray coding method. The circuit and layout designs of Time to Digital Converter (TDC) with same frequency coding mode are implemented in TSMC 0.35m CMOS process. The test results of the Multi Project Wafer (MPW) chip show that BER of the same frequency coding mode is effectively reduced compared with traditional encoding modes under the same conditions.-
Key words:
- Coding circuit /
- Time to Digital Converter (TDC) /
- Bit Error Rate (BER) /
- Data sampling /
-
LI Qianfeng and HU Qingsheng. A 10ps 500MS/s two-channel Vernier TDC in 0.18 CMOS technology[C]. IEEE Workshop on Advanced Research and Technology in Industry Applications (WARTIA), Ottawa, Canada, 2014: 1268-1271. doi: 10.1109/WARTIA.2014.6976513. BREZINA C, FU Y, ZAPPON F, et al. GOSSIPO-4: evaluation of a Novel PLL-based TDC-technique for the readout of gridpix-detectors[J]. IEEE Transactions on Nuclear Science, 2014, 61(2): 1007-1014. doi: 10.1109/ TNS.2014.2301141. UCHIDA Daisuke, IKEBE Masayuki, MOTOHISA Junichi, et al. A 12-bit, 5.5-W single-slope ADC using intermittent working TDC with multi-phase clock signals[C]. International Conference on Electronics, Circuits and Systems (ICECS), Marseille, France, 2014: 770-773. doi: 10.1109/ICECS. 2014.7050099. KALISZ J, SZPLET R, PELKA R, et al. Single-chip interpolating time counter with 200-ps resolution and 43-s range[J]. IEEE Transactions on Instrumentation and Measurement, 1997, 46(4): 851-856. doi: 10.1109/19.650787. KATOH Kentaroh, DOI Yoshihito, ITO Satoshi, et al. An analysis of stochastic self-calibration of TDC using two ring oscillators[C]. IEEE Conference on Asian Test Symposium (ATS), Jiaosi Township, China, 2013: 140-146. doi: 10.1109/ ATS.2013.35. URANO Yuki, YUN WonJoo J, KURODA Tadahiro, et al. A 1.26 mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL[C]. International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013: 1576-1579. doi: 10.1109/ISCAS.2013.6572161. 姚茂群, 張立彬, 耿亮. 電流型 CMOS 脈沖 D 觸發(fā)器設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2014, 36(9): 2278-2282. doi: 10.3724/ SP.J.1146.2013.00343. YAO Maoqun, ZHAGN Libin, and GENG Liang. Design of current-mode CMOS pulse-triggered D flip-flops[J]. Journal of Electronics Information Technology, 2014, 36(9): 2278- 2282. doi: 10.3724/SP.J.1146.2013.00343. 歐慶于, 羅芳, 吳曉平. 基于 NCL 電路的抗故障攻擊設(shè)計(jì)研究[J]. 電子與信息學(xué)報(bào), 2014, 36(7): 1648-1655. doi: 10.3724/ SP.J.1146.2013.00750. OU Qingyu, LUO Fang, and WU Xiaoping. The research on countermeasure against fault attacks for NCL circuits[J]. Journal of Electronics Information Technology, 2014, 36(7): 1648-1655. doi: 10.3724/SP.J.1146.2013.00750. PELKA R, KALISZ J, and SZPLET R. Nonlinearity correction of the integrated time-to-digital converter with direct coding[J]. IEEE Transactions on Instrumentation and Measurement, 1997, 46(2): 449-453. doi: 10.1109/19.571882. POLAT and MANZAK A. Design and analysis of low power Carbon Nanotube Field Effect Transistor (CNFET) D Flip-Flops (DFFs)[C]. International Conference on Computer Research and Development (ICCRD), Shanghai, China, 2011, 3: 399-401. doi: 10.1109/ICCRD.2011.5764223. TAIT A N and PRUCNAL P R. Applications of wavelength-fan-in for high-performance distributed processing systems[C]. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, Paris, France, 2014: 177-178. doi: 10.1109/NANOARCH.2014. 6880485. JIN Wei, LU Sheng, HE Weifeng, et al. Robust design of sub-threshold flip-flop cells for wireless sensor network[C]. International Conference on VLSI and System-on-Chip (VLSI-SoC), Hong Kong, China, 2011: 440-443. doi: 10.1109/VLSISoC.2011.6081623. SALIGRAM Rakshith and RAKSHITH T R. Contemplation of synchronous Gray Code counter and its variants using reversible logic gates[C]. IEEE Conference on Information Communication Technologies (ICT), JeJu Island, Korea, 2013: 661-665. doi: 10.1109/CICT.2013.6558177. KALISZ J, PAWLOWSKI M, and PELKA R. Error analysis and design of the Nutt time-interval digitiser with picosecond resolution[J]. Journal of Physics E: Scientific Instruments, 1987, 20(11): 1330-1341. REDANT Tom, STUBBE Frederic, and DEHAENE Wim. A low power time-of-arrival ranging front end based on a 8-channel 2.2 mW, 53ps single-shot-precision time-to-digital converter[C]. IEEE Conference on Solid State Circuits, Jeju, Korea, 2011: 321-324. doi: 10.1109/ASSCC.2011.6123578. HENZLER Stephan. Time-to-Digital Converters[M]. London, Springer Science Business Media, 2010: 25-31. -
計(jì)量
- 文章訪問(wèn)數(shù): 1188
- HTML全文瀏覽量: 101
- PDF下載量: 361
- 被引次數(shù): 0