基于鏡像對稱參考切片的多掃描鏈測試數(shù)據(jù)壓縮方法
doi: 10.11999/JEIT141146 cstr: 32379.14.JEIT141146
基金項目:
國家自然科學基金(61472123, 60673085)資助課題
Test Data Compression Method for Multiple Scan Chain Based on Mirror-symmetrical Reference Slices
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摘要: 為了減少測試數(shù)據(jù)和測試時間,該文提出一種基于鏡像對稱參考切片的多掃描鏈測試數(shù)據(jù)壓縮方法。采用兩個相互鏡像對稱的參考切片與掃描切片做相容性比較,提高了相容概率。若掃描切片與參考切片相容,只需要很少的幾位編碼就可以表示這個掃描切片,并且可以并行載入多掃描鏈;若不相容,參考切片被該掃描切片替換。提出一種最長相容策略,用來處理掃描切片與參考切片同時滿足多種相容關系時的選取問題。根據(jù)Huffman編碼原理確定不同相容情況的編碼碼字,可以進一步提高測試數(shù)據(jù)的壓縮率。實驗結(jié)果表明所提方法的平均測試數(shù)據(jù)壓縮率達到了69.13%。
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關鍵詞:
- 測試數(shù)據(jù)壓縮 /
- 多掃描鏈 /
- 相容性 /
- 參考切片 /
- 掃描切片
Abstract: In order to reduce test data and test time, a test data compression method for multiple scan chain which bases on mirror-symmetrical reference slices is proposed. This method uses two mutually mirror-symmetrical reference slices for compatibility comparison with scan slice, that improves the compression ratio. If the scan slice is compatible to one of the reference slices, only a few bits are needed to encode it and can be loaded in parallel. Otherwise, the scan slice will replace one reference slice. A longest compatibility strategy is proposed when the scan slice and reference slice satisfy more compatible relationship. It can further improve the test compression ratio to determine the code word according to the different compatibility frequency statistics situations. The experimental results show that the average compression rate of the proposed scheme reaches 69.13%.-
Key words:
- Test data compression /
- Multiple scan chain /
- Compatibility /
- Reference slice /
- Scan slice
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Touba N A. Survey of test vector compression techniques[J]. Design Test of Computers, 2006, 23(4): 294-303. Chandra A and Chakrabarty K. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes[J]. IEEE Transactions on Computers, 2003, 52(8): 1076-1088. Gonciari P T, AI-Hashimi B M, and Nicolici N. Variable- length input huffman coding for system-on-a-chip test[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(6): 783-789. Kavousianous X, Kalligeros E, and Nikolos D. Optimal selective huffman coding for test-data compression[J]. IEEE Transaction on Computers, 2007, 56(8): 1146-1152. 詹文法, 梁華國, 時峰, 等. 一種共游程碼的測試數(shù)據(jù)壓縮方法[J]. 計算機研究與發(fā)展, 2008, 45(10): 1646-1653. Zhan Wen-fa, Liang Hua-guo, Shi Feng, et al.. A scheme of test data compression based on sharing run length code[J]. Journal of Computer Research and Development, 2008, 45(10): 1646-1653. 馬會, 鄺繼順, 馬偉. 基于一位標識的測試向量混合編碼壓縮方法[J]. 電子測量與儀器學報, 2013, 27(4): 312-318. Ma Hui, Kuang Ji-shun, and Ma Wei. Hybrid coding compression method of test vector based on an identification [J]. Journal of Electronic Measurement and Instrument, 2013, 27(4): 312-318. Sismanoglou P and Nikolos D. Input test data compression based on the reuse of parts of dictionary entries: static and dynamic approaches[J]. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 2013, 32(11): 1762-1775. Sismanoglou P and Nikolos D. Test data compression based on reuse and bit-flipping of parts of dictionary entries[C]. Proceedings of 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems, Warsaw, Poland, 2014: 110-115. 劉杰, 易茂祥, 朱勇. 采用字典詞條衍生模式的測試數(shù)據(jù)壓縮[J]. 電子與信息學報, 2012, 34(1): 231-235. Liu Jie, Yi Mao-xiang, and Zhu Yong. Test data compression using entry derivative mode of dictionary[J]. Journal of Electronics Information Technology, 2012, 34(1): 231-235. Han Yin-he, Hu Yu, Li Hua-wei, et al.. Ripad and energy- efficient testing for embedded cores[C]. Proceedings of 13th IEEE Asian Test Symposium, Washington DC, USA, 2004: 8-13. Ruan X and Katti R. An efficient data-independent technique for compressing test vectors in systems-on-a- chip[C]. Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, 2006: 153-158. Lin Shih-ping, Lee Chunag-len, Chen Jwu-e, et al.. A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2007, 15(7): 767-776. Tyszer J, Filipek M, Mrugalski G, et al.. New test compression scheme based on low power BIST[C]. Proceedings of 18th IEEE European Test Symposium, Avignon, France, 2013: 1-6. Chloupek M, Jenicek J, Novak O, et al.. Test pattern decompression in parallel scan chain architecture[C]. Proceedings of 16th International Symposium on Design and Diagnostics of Electronic Circuits Systems, Karlovy Vary , Czech Republic, 2013: 219-223. Yi Mao-xiang, Liang Hua-guo, Zhang Lei, et al.. A novel x-ploiting strategy for improving performance of test data compression[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(2): 324-329. -
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