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一種模擬電路自動綜合中的數(shù)據(jù)陣列描述方法

高雪蓮,  石寅

高雪蓮, 石寅. 一種模擬電路自動綜合中的數(shù)據(jù)陣列描述方法[J]. 電子與信息學報, 2006, 28(7): 1340-1344.
引用本文: 高雪蓮, 石寅. 一種模擬電路自動綜合中的數(shù)據(jù)陣列描述方法[J]. 電子與信息學報, 2006, 28(7): 1340-1344.
Gao Xue-lian, Shi Yin. A Data Array Description Method in Automatic Synthesis of Analog Circuit[J]. Journal of Electronics & Information Technology, 2006, 28(7): 1340-1344.
Citation: Gao Xue-lian, Shi Yin. A Data Array Description Method in Automatic Synthesis of Analog Circuit[J]. Journal of Electronics & Information Technology, 2006, 28(7): 1340-1344.

一種模擬電路自動綜合中的數(shù)據(jù)陣列描述方法

A Data Array Description Method in Automatic Synthesis of Analog Circuit

  • 摘要: 該文提出模擬電路的數(shù)據(jù)陣列描述方法及其與描述方法協(xié)同工作的電路生成規(guī)則。其中，數(shù)據(jù)陣列表述融入了成功的設計經(jīng)驗，并且能夠有效地解決多端器件的電路連接問題；電路生成規(guī)則確保在不出現(xiàn)無效電路結構的前提下，生成高質量的運放電路結構。這種新的生成式電路設計方法克服了選擇式拓撲設計方法依賴設計者經(jīng)驗和生成式拓撲設計方法難以利用電路設計成功經(jīng)驗的局限。從若干經(jīng)典子電路結構開始運放電路自動生成，保證了生成電路拓撲的質量。論文以運放電路為例，利用該數(shù)據(jù)陣列描述方法和電路生成規(guī)則，實驗生成兩個性能特點不同的運放電路，并對電路參數(shù)進行合理確定和電路仿真。
    Abstract: This paper presents an analog circuit data array description method and circuit-constructing rules that coordinately work with description language. With the prerequisite of no invalid circuit structure, circuit-constructing rules create high quality op-amp circuit structure. This new technique, starting from classic sub-circuit model, automatically creating op-amp circuit, guarantees the quality of circuit construction. Results are reported to validate the effectiveness of this approach for construction-design automation of op-amp circuit.
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  • Goh C, li Y. GA automated design and synthesis of analog circuitswith practical constraints, 2001. Proceedings of the 2001Congress on Evolutionary Computation, Seoul, Korea, 27-30 May,2001, Vol. 1: 170 . 177 .[2]Papa G, Silc J. Automatic large-scale integrated circuit synthesisusing allocation-based scheduling algorithm, Microprocessorsand Microsystems, 2002, 26(3): 139 . 147.[3]Koh H Y, Sequin C H, Gray P R. OPASYN：A compiler forCMOS operational amplifiers[J].IEEE Trans. on Computer-AidedDesign of Integrated Circuits and Systems.1990, 9(2):113-[4]Gupta S K, Hasan M M. KANSYS: A CAD tool for analog circuitsynthesis. 9th International Conference on VLSI Design,Bangalore, India, Jan. 1996: 333 . 334.[5]El-Turky F, Perry E E. BLADES: An artificial intelligenceapproach to analog circuit design[J].IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems.1989, 8(6):680-[6]Makris C A, et al.. CHIPAIED: A new approach to analogueintegrated circuit design. IEE Colloquium on Analogue VLSI,London,UK,10 May, 1990: 1/1 . 111.[7]Lohn J D, Colombano S P. A circuit representation technique forautomated circuit design. IEEE Trans. on EvolutionaryComputation, 1999, 3(3): 205 . 219.[8]Prakobwaitayakit K, Fujii N. A neural network approach to circuittopology generator. The 2000 IEEE Asia-Pacific Conference onCircuits and Systems, Tianjin, China, 4-6 Dec., 2000: 93 . 96.
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  • 文章訪問數(shù):  1975
  • HTML全文瀏覽量:  104
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  • 被引次數(shù): 0
出版歷程
  • 收稿日期:  2004-11-25
  • 修回日期:  2005-06-07
  • 刊出日期:  2006-07-19

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