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基于電路狀態(tài)信息和沖突分析的部分掃描設(shè)計(jì)

向東 劉鑫 徐奕

向東, 劉鑫, 徐奕. 基于電路狀態(tài)信息和沖突分析的部分掃描設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2004, 26(1): 124-130.
引用本文: 向東, 劉鑫, 徐奕. 基于電路狀態(tài)信息和沖突分析的部分掃描設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2004, 26(1): 124-130.
Xiang Dong, Liu Xin, Xu Yi. Partial Scan Design Based on Circuit State Information and Conflict Analysis[J]. Journal of Electronics & Information Technology, 2004, 26(1): 124-130.
Citation: Xiang Dong, Liu Xin, Xu Yi. Partial Scan Design Based on Circuit State Information and Conflict Analysis[J]. Journal of Electronics & Information Technology, 2004, 26(1): 124-130.

基于電路狀態(tài)信息和沖突分析的部分掃描設(shè)計(jì)

Partial Scan Design Based on Circuit State Information and Conflict Analysis

  • 摘要: 該文提出了一種割斷關(guān)鍵回路的方法來選擇掃描觸發(fā)器。該方法在選擇一定數(shù)量的掃描觸發(fā)器后,采用邏輯模擬更新電路的狀態(tài)信息,這樣可以得到更為精確的可測試性信息。當(dāng)電路中的關(guān)鍵回路割斷后,轉(zhuǎn)向消除沖突的處理,而不是降低時(shí)序深度。該方法致力于消除沖突,并使用了一種基于沖突分析的測度conflict。足夠的實(shí)驗(yàn)結(jié)果表明該方法是非常有效的。
  • Corno F, Prinetto P, Sonza Reorda M, Violante M. Exploiting symbolic techniques for partial scan flip-flop selection. Proc. of IEEE Design Automation and Test in Europe, Paris, France,Feb. 23-26, 1998: 670-677.[2]Cheng K T, Agrawal V D. A partial scan method for sequential circuits with feedback[J].IEEE Trans. on Computers.1990, 39(4):544-548[3]Chickermane V, Patel J H. An optimization based approach to the partial scan design problem.Proc. of IEEE Int. Test Conf., Washington, DC, Sep. 10-14, 1990: 377-386.[4]Gupta R, Gupta R, Breuer M A. The BALLAST methodology for structured partial scan design[J].IEEE Trans. on Computers.1990, 39(4):538-544[5]Parihk P S, Abramovici M. Testability-based partial scan analysis[J].J. of Electronic Testing.1995,7:61-70[6]Sharma S, Hsiao M. Combination of structural and state analysis for partial scan. Proc. of Int.VLSI Design Conf., Bangalore, India, Jan. 3-7, 2001: 134-139.[7]Saund G S, Hsiao M S, Patel J H. Partial scan beyond cycle cutting. Proc. of IEEE Int. Symp.on Fault-Tolerant Computing, Seattle, Washington, USA, Jun. 24-27, 1997: 320-328.[8]Xiang D, Venkataraman S, Fuchs W K, Patel J H. Partial scan design based on circuit statc information. Proc. of ACM/IEEE Design Automation Conference, Las Vegas, USA, .Junc 1996:807-812.[9]Xiang D, Xu Y, Fujiwara H. Non-scan design for testability for synchronous sequential circuits based on conflict resolution. Accepted to appear in IEEE Trans. on Computers.[10]Xiang D, Fujiwara H. Handling the pin overhead problem of DFTs for high quality and at-speed tests[J].IEEE Trans. on Computer-Aided Design of ICAS.2002, 21(9):1105-1113[11]Kalla P, Ciesielski M J. A comprehensive approach to the partial scan problem using implicit state enumeration[J].IEEE Trans. on Computer-Aided Design of ICAS.2002, 21(7):810-826[12]Niermann T M, Patel J H. HITEC: A test generation package for sequential circuits. Proc. of European Conf. Design Automation, Amsterdam, The Netherlands, Feb. 25-28, 1991: 214-218.
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出版歷程
  • 收稿日期:  2002-08-14
  • 修回日期:  2002-12-31
  • 刊出日期:  2004-01-19

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