模擬集成電路的測試節(jié)點選擇
Test Point Selection for Analog Integrated Circuit
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摘要: 如何尋求一個最佳的測試節(jié)點或測試矢量集是模擬集成電路的故障診斷中的重要問題。該文提出了一種基于可測性測度計算的測試節(jié)點選擇方法。利用行列式判決圖,可以有效而準確地求得被測電路傳輸函數(shù)的符號表達式和計算出其可測性測度。該方法完全消除了由數(shù)字方法引入的不可避免的舍入誤差,并能處理中、大規(guī)模的集成電路.
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關(guān)鍵詞:
- 可測性測度; 行列式判決圖; 模擬集成電路
Abstract: How to select an optimum set of test points or test vectors has become very critical to analog integrated circuit fault diagnosis. A test point selection method based on testability measure is presented in this paper. Using Determinant Decision Diagrams (DDDs), symbolic transfer functions of circuit under test are constructed and its testability measure can be calculated exactly and efficiently. This method eliminates completely the unavoidable round-off errors introduced by numerical algorithms and can handle moderate or large integrated circuits. -
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