基于FPGA的數(shù)字化正交解調(diào)接收機(jī)最優(yōu)設(shè)計(jì)
Optimization Design of Digital Quadrature Demodulation Receiver Based on FPGA
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摘要: 結(jié)合抽取濾波器的多項(xiàng)濾波結(jié)構(gòu)，在一定條件下，推導(dǎo)出了一種含抽取正交解調(diào)接收機(jī)最優(yōu)結(jié)構(gòu)設(shè)計(jì)方法。在FPGA乘法器資源相同的條件下，采用最優(yōu)結(jié)構(gòu)設(shè)計(jì)的接收機(jī)內(nèi)部FIR濾波器階數(shù)比直接實(shí)現(xiàn)形式高了近4倍。最后給出了設(shè)計(jì)實(shí)例。
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關(guān)鍵詞:
- 正交解調(diào);FPGA;多項(xiàng)濾波
Abstract: Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure. With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly 4 times than it implemented in direct way. Finally the design instance is given. -
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