IC制造中真實缺陷輪廓模型的比較
COMPARISON OF MODELS OF REAL DEFECT OUTLINES IN THE IC MANUFACTURING PROCESS
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摘要: 本文對現(xiàn)有的IC制造中真實缺陷輪廓的建模方法進行了比較,得到了一些有意義的結果。該結果為進行有效的集成電路(IC)成品率預報及故障分析提供了有益的借鑒。Abstract: The approaches to model the real defect outlines in the IC manufacturing process are compared and some useful conclusions are obtained. The results obtained in this paper will be helpful for yield prediction and fault analysis of IC.
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Ferguson F J, Shen J P. Extraction and simulation of realistic CMOS faults using inductive fault analysis. Presented at the Internat. Test Conf., Washington, DC: September 1988, 475-484.[2]Ferris Prabhu A V. Modeling the critical area in yield forecasts. IEEE J. of Solid-State Circuit, SC-20(4): 874-878.[3]Maly W. Computer-aided design for VLSI circuit manufacturability[J].Proc. IEEE.1990, 78(2):356-[4]392.[5]de Gyvez J P, Chennian D. IC defect sensitivity for footprint type spot defects[J].IEEE Trans. on Computer-Aided Design.1992, 11(5):638-658[6]Cristopher Hess, Albrecht Strole. Modeling of real defect outlines for defect size distribution and yield prediction. Proc. IEEE Int. Conference on Microelectronic Test Structures, Sitges, Barcelona, Spain: March 1993, Vol 6, 75-80.[7]姜曉鴻,郝躍,等.IC制造中的真實缺陷輪廓表征方法研究.電子學報(已錄用,待發(fā)表). -
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