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驗證碼

使用布爾可滿足性的組合電路等價性驗證算法

鄭飛君,  嚴(yán)曉浪,  葛海通,  楊軍

鄭飛君, 嚴(yán)曉浪, 葛海通, 楊軍. 使用布爾可滿足性的組合電路等價性驗證算法[J]. 電子與信息學(xué)報, 2005, 27(4): 651-654.
引用本文: 鄭飛君, 嚴(yán)曉浪, 葛海通, 楊軍. 使用布爾可滿足性的組合電路等價性驗證算法[J]. 電子與信息學(xué)報, 2005, 27(4): 651-654.
Zheng Fei-jun, Yan Xiao-lang, Ge Hai-tong, Yang Jun . Using Boolean Satisfiability for Combinational Equivalence Checking[J]. Journal of Electronics & Information Technology, 2005, 27(4): 651-654.
Citation: Zheng Fei-jun, Yan Xiao-lang, Ge Hai-tong, Yang Jun . Using Boolean Satisfiability for Combinational Equivalence Checking[J]. Journal of Electronics & Information Technology, 2005, 27(4): 651-654.

使用布爾可滿足性的組合電路等價性驗證算法

Using Boolean Satisfiability for Combinational Equivalence Checking

  • 摘要: 該文提出了一種使用布爾可滿足性SAT的新穎組合電路等價性驗證技術(shù)。算法是在聯(lián)接電路(Miter circuit)中進(jìn)行推理來簡化驗證問題，推理中使用了與／非圖結(jié)構(gòu)簡化、BDD擴展、隱含學(xué)習(xí)多種方法，最后使用有效SAT解算器zChaff解決驗證任務(wù)。該算法綜合了BDD和SAT的優(yōu)點，限制BDD構(gòu)建大小避免了內(nèi)存爆炸，推理簡化減小了SAT搜索空間。ISCAS85電路實驗結(jié)果表明了本算法的有效性。
    Abstract: In this paper, a new combinational equivalence checking approach using Boolean Satisfiability is proposed. The algorithm uses several methods to reduce the space of the SAT reasoning first, those methods are AND/INVERTER graph transformation, BDD propagation and implication learning, CNF-based SAT solver zChaff is used to solve the verification task. The algorithm combines the advantages of both BDD and SAT, BDDs size is limited to avoid memory explosion problem and structural reduction is applied to reduce the search space of SAT. The efficiency of the proposed approach is shown through its application on the ISCAS85 benchmark circuits.
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  • Bryant R E. Graph-based algorithms for Boolean function manipulation[J].IEEE Trans. on Computers.1986, C-35(8):677-[2]Brand D. Verification of large synthesized designs. ICCAD, San Jose, CA, 1993:534 - 537.[3]Andreas Kuehlmann, Florian Krohm. Equivalence checking using cuts and heaps. Design Automation Conference, Anaheim, CA,1997:263 - 268.[4]Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S. Chaff:Engineering an efficient SAT solver. Design Automation Conference, Las Vegas, 2001:530 - 535.Goldberg E I, Prasad M R, Brayton R K. Using SAT for combinational equivalence checking. Design Automation and Test in Europe, UK, 2001:114 - 121.[5]Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K Ganai. Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Trans. on CAD, 2002,C-21(12): 1377- 1394.[6]Malay K Ganai, Lintao Zhang, Pranav Ashar, Aarti Gupta, Sharad Malik. Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT. Design Automation Conference, New Orleans, 2002:747 - 750.[7]Fabio Somenzi. CUDD: CU Decision Diagram package release 2.3.1( http:∥v lsi.colorado.edu/～ fabio/2001 ).[8]Matsunaga Y. An efficient equivalence checker for combinational circuits. Design Automation Conference, Las Vegas, 1996:629 - 634.
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出版歷程
  • 收稿日期:  2003-11-04
  • 修回日期:  2004-03-02
  • 刊出日期:  2005-04-19

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