基于線性與或門的新型超高速數(shù)字電路
THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES
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摘要: 本文指出了線性與或門與發(fā)射極功能邏輯(EFL)的聯(lián)系,通過理論計算與PSPICE模擬證明了線性與或門的極高速工作特性和可多級級聯(lián)工作能力。在對線性與或門所需配用的高速開關(guān)分析基礎(chǔ)上,設(shè)計了兩種ECL電路。本文還討論了應(yīng)用線性與或門設(shè)計超高速數(shù)字電路的準則以及有關(guān)的組合和時序電路設(shè)計實例。
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關(guān)鍵詞:
- 線性與或門; 超高速數(shù)字電路; 多元邏輯電路
Abstract: The paper reveals the relation between linear AND-OR gate and the Emitter Function Logic (EFL). With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of Emitter Coupled Logic (ECL) circuits are designed. The paper also discusses the design principle of super-high-speed digital circuits and some examples of combinational and sequential circuits using linear AND-OR gate are given. -
王守覺,等.電子學報,1987,6(2): 43-51.[2]王守覺,等.電子學報,1983,11(5): 9-16.[3]Skokan I E. IEEEJ. of SC, 1973, SC-8(5): 356-361.[4]Elmasry M 1. Digital Dipolar Integrated Circuits. New York: John Wiley Sons, Inc., 1989, Ch.6.[5]石寅.連續(xù)邏輯高速門陣列研究:[博士論文].北京:中國科學院半導(dǎo)體研究所,1986.[6]Muroga S. VLSI System Design. New York: John WileySons, Inc, 1982, Ch. 3.[7]Xunwei Wu(吳訓威),Zhuan Zhang(章專).Int. J[J].Electron.1991, 71(6):1023-1035[8]王守覺,石寅,朱榮華.半導(dǎo)體學報,1987,8(5): 466-473.[9]馮宏娟.DYL電路的研究新進展.中國第一屆多值邏輯電路與系統(tǒng)學術(shù)會議.青島:1991. -
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